iotg->hsm.a_clr_err = 0;
if (iotg->otg.state == OTG_STATE_A_IDLE) {
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
pm_runtime_get(pnw->dev);
}
hsm->a_bus_req = 1;
/* Prevent device enter D0i1 or S3*/
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
pm_runtime_get(pnw->dev);
iotg->otg.state = OTG_STATE_A_IDLE;
hsm->a_bus_req = 1;
/* Prevent device enter D0i1 or S3*/
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
pm_runtime_get(pnw->dev);
iotg->otg.state = OTG_STATE_A_IDLE;
*/
/* disallow D3 or D0i3 */
pm_runtime_get(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_B_WAIT_ACON;
penwell_otg_add_timer(TB_ASE0_BRST_TMR);
} else
/* allow D3 and D0i3 */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
+#else
+ pm_relax(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_B_IDLE;
} else if (hsm->a_conn) {
/* Move to B_HOST state, A connected */
/* allow D3 and D0i3 in A_WAIT_BCON */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
+#else
+ pm_relax(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_B_PERIPHERAL;
} else if (hsm->id == ID_ACA_C) {
/* Make sure current limit updated */
/* allow D3 and D0i3 in A_WAIT_BCON */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
+#else
+ pm_relax(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_B_IDLE;
} else if (!hsm->b_bus_req || !hsm->a_conn
|| hsm->test_device) {
/* allow D3 and D0i3 in A_WAIT_BCON */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
+#else
+ pm_relax(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_B_PERIPHERAL;
} else if (hsm->id == ID_ACA_C) {
/* Make sure current limit updated */
/* Decrement the device usage counter */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
+#else
+ pm_relax(pnw->dev);
+#endif
} else if (hsm->id == ID_ACA_A) {
penwell_otg_update_chrg_cap(CHRG_ACA, CHRG_CURR_ACA);
/* allow D3 and D0i3 in A_WAIT_BCON */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
+#else
+ pm_relax(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_WAIT_BCON;
/* allow D3 and D0i3 in A_WAIT_BCON */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
/* at least give some time to USB HOST to enumerate
* devices before trying to suspend the system*/
wake_lock_timeout(&pnw->wake_lock, 5 * HZ);
+#else
+ pm_relax(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_WAIT_BCON;
}
/* disallow D3 or D0i3 */
pm_runtime_get(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
} else if (!hsm->a_vbus_vld) {
/* Move to A_VBUS_ERR state, over-current detected */
penwell_otg_phy_low_power(1);
/* disallow D3 or D0i3 */
pm_runtime_get(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_VBUS_ERR;
} else if (hsm->b_conn) {
/* Move to A_HOST state, device connected */
/* disallow D3 or D0i3 */
pm_runtime_get(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
} else if (hsm->test_device && hsm->tst_maint_tmout) {
/* disallow D3 or D0i3 */
pm_runtime_get(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_IDLE;
} else if (!hsm->a_vbus_vld) {
/* Move to A_VBUS_ERR state */
/* disallow D3 or D0i3 */
pm_runtime_get(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_VBUS_ERR;
} else if (!hsm->a_bus_req && iotg->otg.host->b_hnp_enable) {
/* Move to A_SUSPEND state */
/* disallow D3 or D0i3 */
pm_runtime_get(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_SUSPEND;
} else if (!hsm->b_conn && hsm->test_device
&& hsm->otg_vbus_off) {
/* disallow D3 or D0i3 */
pm_runtime_get(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&pnw->wake_lock);
+#else
+ pm_stay_awake(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
} else if (!hsm->b_conn) {
/* allow D3 and D0i3 in A_WAIT_BCON */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
+#else
+ pm_relax(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_WAIT_BCON;
} else if (!hsm->b_conn && pnw->iotg.otg.host->b_hnp_enable) {
/* Move to A_PERIPHERAL state, HNP */
/* allow D3 and D0i3 in A_HOST */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
+#else
+ pm_relax(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_HOST;
} else if (hsm->id == ID_ACA_A) {
penwell_otg_update_chrg_cap(CHRG_ACA, CHRG_CURR_ACA);
/* allow D3 and D0i3 in A_WAIT_BCON */
pm_runtime_put(pnw->dev);
+#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&pnw->wake_lock);
+#else
+ pm_relax(pnw->dev);
+#endif
iotg->otg.state = OTG_STATE_A_WAIT_BCON;
} else if (hsm->id == ID_A && hsm->b_bus_suspend) {
if (!timer_pending(&pnw->hsm_timer))
spin_lock_init(&pnw->iotg.hnp_poll_lock);
spin_lock_init(&pnw->notify_lock);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock_init(&pnw->wake_lock, WAKE_LOCK_SUSPEND, "pnw_wake_lock");
+#else
+ device_init_wakeup(pnw->dev, 1);
+#endif
init_timer(&pnw->hsm_timer);
init_timer(&pnw->bus_mon_timer);
/* disable OTGSC interrupt as OTGSC doesn't change in reset */
writel(0, pnw->iotg.base + CI_OTGSC);
+#ifdef CONFIG_HAS_WAKELOCK
wake_lock_destroy(&pnw->wake_lock);
-
+#else
+ device_set_wakeup_enable(pnw->dev, 0);
+#endif
if (pdev->irq)
free_irq(pdev->irq, pnw);
if (pnw->cfg_region)