IBM Z: Fix PR96456

The testcase failed because our backend refuses to generate vector
compare instructions for signaling operators with -fno-trapping-math
-fno-finite-math-only.

gcc/ChangeLog:

	PR target/96456
	* config/s390/s390.h (TARGET_NONSIGNALING_VECTOR_COMPARE_OK): New
	macro.
	* config/s390/vector.md (vcond_comparison_operator): Use new macro
	for the check.

gcc/testsuite/ChangeLog:

	PR target/96456
	* gcc.target/s390/pr96456.c: New test.

diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index e4ef63e..ec5128c 100644 (file)
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -175,6 +175,11 @@ enum processor_flags
 #define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS 0
 #endif
 
+/* Evaluate to true if it is ok to emit a non-signaling vector
+   comparison.  */
+#define TARGET_NONSIGNALING_VECTOR_COMPARE_OK \
+  (TARGET_VX && !TARGET_VXE && (flag_finite_math_only || !flag_trapping_math))
+
 #ifdef HAVE_AS_MACHINE_MACHINEMODE
 #define S390_USE_TARGET_ATTRIBUTE 1
 #else

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 08f2d4c..131bbda 100644 (file)
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -622,7 +622,7 @@
     case GT:
     case LTGT:
       /* Signaling vector comparisons are supported only on z14+.  */
-      return TARGET_Z14;
+      return TARGET_VXE || TARGET_NONSIGNALING_VECTOR_COMPARE_OK;
     default:
       return true;
     }
@@ -1534,7 +1534,7 @@
   [(set (match_operand:<tointvec>         0 "register_operand" "=v")
        (gt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
                       (match_operand:VFT 2 "register_operand" "v")))]
-  "TARGET_VX && !TARGET_VXE && flag_finite_math_only"
+  "TARGET_NONSIGNALING_VECTOR_COMPARE_OK"
   "<vw>fch<sdx>b\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
 
@@ -1551,7 +1551,7 @@
   [(set (match_operand:<tointvec>         0 "register_operand" "=v")
        (ge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
                       (match_operand:VFT 2 "register_operand" "v")))]
-  "TARGET_VX && !TARGET_VXE && flag_finite_math_only"
+  "TARGET_NONSIGNALING_VECTOR_COMPARE_OK"
   "<vw>fche<sdx>b\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
 

diff --git a/gcc/testsuite/gcc.target/s390/pr96456.c b/gcc/testsuite/gcc.target/s390/pr96456.c
new file mode 100644 (file)
index 0000000..ea9e9cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/pr96456.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -std=gnu99 -ffast-math -fno-finite-math-only -march=z13" } */
+
+int b, c, d;
+double *e;
+int f() {
+  double *a = a;
+  int g = d, f = c, h = b;
+  if (__builtin_expect(f, 0))
+    for (; g < h; g++)
+      e[g] = (int)(a[g] >= 0.0 ? g + 0.99999999 : a[g]);
+  return 0;
+}