arm64: dts: ls1028a: add crypto node

LS1028A has a SEC v5.0 compatible security engine.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 68e1eaf..de6ef39 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -17,6 +17,7 @@
        compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
 
        aliases {
+               crypto = &crypto;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index c1b58a5..9fb9113 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -16,6 +16,7 @@
        compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
 
        aliases {
+               crypto = &crypto;
                serial0 = &duart0;
                serial1 = &duart1;
        };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 8ba1e03..80e8976 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -388,6 +388,45 @@
                                     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               crypto: crypto@8000000 {
+                       compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+                       fsl,sec-era = <10>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x00 0x8000000 0x100000>;
+                       reg = <0x00 0x8000000 0x0 0x100000>;
+                       interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-coherent;
+
+                       sec_jr0: jr@10000 {
+                               compatible = "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg     = <0x10000 0x10000>;
+                               interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       sec_jr1: jr@20000 {
+                               compatible = "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg     = <0x20000 0x10000>;
+                               interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       sec_jr2: jr@30000 {
+                               compatible = "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg     = <0x30000 0x10000>;
+                               interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       sec_jr3: jr@40000 {
+                               compatible = "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg     = <0x40000 0x10000>;
+                               interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
                cluster1_core0_watchdog: watchdog@c000000 {
                        compatible = "arm,sp805", "arm,primecell";
                        reg = <0x0 0xc000000 0x0 0x1000>;