return AArch64::LSRVWr;
case TargetOpcode::G_ASHR:
return AArch64::ASRVWr;
+ case TargetOpcode::G_SDIV:
+ return AArch64::SDIVWr;
+ case TargetOpcode::G_UDIV:
+ return AArch64::UDIVWr;
default:
return GenericOpc;
}
return AArch64::LSRVXr;
case TargetOpcode::G_ASHR:
return AArch64::ASRVXr;
+ case TargetOpcode::G_SDIV:
+ return AArch64::SDIVXr;
+ case TargetOpcode::G_UDIV:
+ return AArch64::UDIVXr;
default:
return GenericOpc;
}
case TargetOpcode::G_SHL:
case TargetOpcode::G_LSHR:
case TargetOpcode::G_ASHR:
+ case TargetOpcode::G_SDIV:
+ case TargetOpcode::G_UDIV:
case TargetOpcode::G_ADD:
case TargetOpcode::G_SUB: {
// Reject the various things we don't support yet.
define void @mul_s32_gpr() { ret void }
define void @mul_s64_gpr() { ret void }
+ define void @sdiv_s32_gpr() { ret void }
+ define void @sdiv_s64_gpr() { ret void }
+
+ define void @udiv_s32_gpr() { ret void }
+ define void @udiv_s64_gpr() { ret void }
+
define void @unconditional_br() { ret void }
define void @load_s64_gpr(i64* %addr) { ret void }
...
---
+# Same as add_s32_gpr, for G_SDIV operations.
+# CHECK-LABEL: name: sdiv_s32_gpr
+name: sdiv_s32_gpr
+isSSA: true
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = SDIVWr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(32) = COPY %w0
+ %1(32) = COPY %w1
+ %2(32) = G_SDIV s32 %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_SDIV operations.
+# CHECK-LABEL: name: sdiv_s64_gpr
+name: sdiv_s64_gpr
+isSSA: true
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = SDIVXr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(64) = COPY %x0
+ %1(64) = COPY %x1
+ %2(64) = G_SDIV s64 %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_UDIV operations.
+# CHECK-LABEL: name: udiv_s32_gpr
+name: udiv_s32_gpr
+isSSA: true
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = UDIVWr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(32) = COPY %w0
+ %1(32) = COPY %w1
+ %2(32) = G_UDIV s32 %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_UDIV operations.
+# CHECK-LABEL: name: udiv_s64_gpr
+name: udiv_s64_gpr
+isSSA: true
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = UDIVXr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(64) = COPY %x0
+ %1(64) = COPY %x1
+ %2(64) = G_UDIV s64 %0, %1
+...
+
+---
# CHECK-LABEL: name: unconditional_br
name: unconditional_br
isSSA: true