[InstCombine] add tests for bitwise logic with bool op; NFC

diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll
index 92e5a75..ec16ffc 100644 (file)
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -1471,6 +1471,16 @@ define i32 @sext_to_sel(i32 %x, i1 %y) {
   ret i32 %r
 }
 
+define <2 x i32> @sext_to_sel_constant_vec(<2 x i1> %y) {
+; CHECK-LABEL: @sext_to_sel_constant_vec(
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[Y:%.*]], <2 x i32> <i32 42, i32 -7>, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %sext = sext <2 x i1> %y to <2 x i32>
+  %r = and <2 x i32> <i32 42, i32 -7>, %sext
+  ret <2 x i32> %r
+}
+
 define <2 x i32> @sext_to_sel_swap(<2 x i32> %px, <2 x i1> %y) {
 ; CHECK-LABEL: @sext_to_sel_swap(
 ; CHECK-NEXT:    [[X:%.*]] = mul <2 x i32> [[PX:%.*]], [[PX]]

diff --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll
index 9fd61eb..6426612 100644 (file)
--- a/llvm/test/Transforms/InstCombine/or.ll
+++ b/llvm/test/Transforms/InstCombine/or.ll
@@ -618,6 +618,16 @@ define i32 @sext_to_sel(i32 %x, i1 %y) {
   ret i32 %r
 }
 
+define <2 x i32> @sext_to_sel_constant_vec(<2 x i1> %y) {
+; CHECK-LABEL: @sext_to_sel_constant_vec(
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[Y:%.*]], <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 42, i32 -7>
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %sext = sext <2 x i1> %y to <2 x i32>
+  %r = or <2 x i32> <i32 42, i32 -7>, %sext
+  ret <2 x i32> %r
+}
+
 define <2 x i32> @sext_to_sel_swap(<2 x i32> %px, <2 x i1> %y) {
 ; CHECK-LABEL: @sext_to_sel_swap(
 ; CHECK-NEXT:    [[X:%.*]] = mul <2 x i32> [[PX:%.*]], [[PX]]