drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set

So WARN in case they're not. It also does not make any sense to
wait_for_vblank at this point.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 709497d..705ed80 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5217,6 +5217,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
        WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
             num_connectors, pipe_name(pipe));
 
+       WARN_ON(I915_READ(PIPECONF(pipe)) &
+               (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
+
+       WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
+
        if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
                return -EINVAL;
 
@@ -5357,8 +5362,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 
        haswell_set_pipeconf(crtc, adjusted_mode, dither);
 
-       intel_wait_for_vblank(dev, pipe);
-
        /* Set up the display plane register */
        I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
        POSTING_READ(DSPCNTR(plane));