CC_MODE (CC_SWP);
CC_MODE (CC_NZC); /* Only N, Z and C bits of condition flags are valid.
(Used with SVE predicate tests.) */
+CC_MODE (CC_NZV); /* Only N, Z and V bits of condition flags are valid. */
CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */
CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */
CC_MODE (CC_C); /* C represents unsigned overflow of a simple addition. */
if (y == const0_rtx && (REG_P (x) || SUBREG_P (x))
&& (code == EQ || code == NE)
&& (mode_x == HImode || mode_x == QImode))
- return CC_NZmode;
+ return CC_Zmode;
/* Similarly, comparisons of zero_extends from shorter modes can
be performed using an ANDS with an immediate mask. */
&& (mode_x == SImode || mode_x == DImode)
&& (GET_MODE (XEXP (x, 0)) == HImode || GET_MODE (XEXP (x, 0)) == QImode)
&& (code == EQ || code == NE))
- return CC_NZmode;
+ return CC_Zmode;
+
+ /* Zero extracts support equality comparisons. */
+ if ((mode_x == SImode || mode_x == DImode)
+ && y == const0_rtx
+ && (code_x == ZERO_EXTRACT && CONST_INT_P (XEXP (x, 1))
+ && CONST_INT_P (XEXP (x, 2)))
+ && (code == EQ || code == NE))
+ return CC_Zmode;
+
+ /* ANDS/BICS/TST support equality and all signed comparisons. */
+ if ((mode_x == SImode || mode_x == DImode)
+ && y == const0_rtx
+ && (code_x == AND)
+ && (code == EQ || code == NE || code == LT || code == GE
+ || code == GT || code == LE))
+ return CC_NZVmode;
+ /* ADDS/SUBS correctly set N and Z flags. */
if ((mode_x == SImode || mode_x == DImode)
&& y == const0_rtx
&& (code == EQ || code == NE || code == LT || code == GE)
- && (code_x == PLUS || code_x == MINUS || code_x == AND
- || code_x == NEG
- || (code_x == ZERO_EXTRACT && CONST_INT_P (XEXP (x, 1))
- && CONST_INT_P (XEXP (x, 2)))))
+ && (code_x == PLUS || code_x == MINUS || code_x == NEG))
return CC_NZmode;
/* A compare with a shifted operand. Because of canonicalization,
}
break;
+ case E_CC_NZVmode:
+ switch (comp_code)
+ {
+ case NE: return AARCH64_NE;
+ case EQ: return AARCH64_EQ;
+ case GE: return AARCH64_PL;
+ case LT: return AARCH64_MI;
+ case GT: return AARCH64_GT;
+ case LE: return AARCH64_LE;
+ default: return -1;
+ }
+ break;
+
case E_CC_NZmode:
switch (comp_code)
{
)
(define_insn "*and<mode>3_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (match_operand:GPI 1 "register_operand" "%r,r")
(match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>"))
(const_int 0)))
;; zero_extend version of above
(define_insn "*andsi3_compare0_uxtw"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:SI (match_operand:SI 1 "register_operand" "%r,r")
(match_operand:SI 2 "aarch64_logical_operand" "r,K"))
(const_int 0)))
)
(define_insn "*and_<SHIFT:optab><mode>3_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (SHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
;; zero_extend version of above
(define_insn "*and_<SHIFT:optab>si3_compare0_uxtw"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:SI (SHIFT:SI
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_si" "n"))
)
(define_insn "*and_one_cmpl<mode>3_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (not:GPI
(match_operand:GPI 1 "register_operand" "r"))
(match_operand:GPI 2 "register_operand" "r"))
;; zero_extend version of above
(define_insn "*and_one_cmplsi3_compare0_uxtw"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:SI (not:SI
(match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "r"))
)
(define_insn "*and_one_cmpl<mode>3_compare0_no_reuse"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (not:GPI
(match_operand:GPI 0 "register_operand" "r"))
(match_operand:GPI 1 "register_operand" "r"))
)
(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (not:GPI
(SHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
;; zero_extend version of above
(define_insn "*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:SI (not:SI
(SHIFT:SI
(match_operand:SI 1 "register_operand" "r")
)
(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (not:GPI
(SHIFT:GPI
(match_operand:GPI 0 "register_operand" "r")
")
(define_insn "*and<mode>_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_Z CC_REGNUM)
+ (compare:CC_Z
(match_operand:SHORT 0 "register_operand" "r")
(const_int 0)))]
""
)
(define_insn "*ands<GPI:mode>_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_Z CC_REGNUM)
+ (compare:CC_Z
(zero_extend:GPI (match_operand:SHORT 1 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
)
(define_insn "*and<mode>3nr_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (match_operand:GPI 0 "register_operand" "%r,r")
(match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>"))
(const_int 0)))]
)
(define_split
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (match_operand:GPI 0 "register_operand")
(match_operand:GPI 1 "aarch64_mov_imm_operand"))
(const_int 0)))
(clobber (match_operand:SI 2 "register_operand"))]
""
[(set (match_dup 2) (match_dup 1))
- (set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ (set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (match_dup 0)
(match_dup 2))
(const_int 0)))]
)
(define_insn "*and<mode>3nr_compare0_zextract"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_Z CC_REGNUM)
+ (compare:CC_Z
(zero_extract:GPI (match_operand:GPI 0 "register_operand" "r")
(match_operand:GPI 1 "const_int_operand" "n")
(match_operand:GPI 2 "const_int_operand" "n"))
)
(define_insn "*and_<SHIFT:optab><mode>3nr_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (SHIFT:GPI
(match_operand:GPI 0 "register_operand" "r")
(match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
)
(define_split
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (SHIFT:GPI
(match_operand:GPI 0 "register_operand")
(match_operand:QI 1 "aarch64_shift_imm_<mode>"))
(clobber (match_operand:SI 3 "register_operand"))]
""
[(set (match_dup 3) (match_dup 2))
- (set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ (set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (SHIFT:GPI
(match_dup 0)
(match_dup 1))
{
int d = a & b;
- /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
if (d <= 0)
return a + c;
else
{
int d = a & 0x99999999;
- /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
- /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
- if (d <= 0)
- return a + c;
- else
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+ if (d > 0)
return b + d + c;
+ else
+ return a + c;
}
int
{
int d = a & (b << 3);
- /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
if (d <= 0)
return a + c;
else
{
s64 d = a & b;
- /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
if (d <= 0)
return a + c;
else
{
s64 d = a & 0xaaaaaaaaaaaaaaaall;
- /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
- /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
- if (d <= 0)
- return a + c;
- else
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+ if (d > 0)
return b + d + c;
+ else
+ return a + c;
}
s64
{
s64 d = a & (b << 3);
- /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
if (d <= 0)
return a + c;
else
{
int d = a & ~b;
- /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
if (d <= 0)
return a + c;
else
{
int d = a & ~(b << 3);
- /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
- if (d <= 0)
- return a + c;
- else
+ /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d > 0)
return b + d + c;
+ else
+ return a + c;
}
typedef long long s64;
{
s64 d = a & ~b;
- /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
if (d <= 0)
return a + c;
else
{
s64 d = a & ~(b << 3);
- /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- if (d <= 0)
- return a + c;
- else
+ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d > 0)
return b + d + c;
+ else
+ return a + c;
}
int
{
int d = a & b;
- /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+" } } */
if (d <= 0)
return 12;
else
{
int d = a & 0x99999999;
- /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
- /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
- if (d <= 0)
- return 12;
- else
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]+, -1717986919" } } */
+ if (d > 0)
return 18;
+ else
+ return 12;
}
int
{
int d = a & (b << 3);
- /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */
if (d <= 0)
return 12;
else
{
s64 d = a & b;
- /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+" } } */
if (d <= 0)
return 12;
else
{
s64 d = a & 0xaaaaaaaaaaaaaaaall;
- /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
- /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]+, -6148914691236517206" } } */
if (d <= 0)
return 12;
else
{
s64 d = a & (b << 3);
- /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- if (d <= 0)
- return 12;
- else
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d > 0)
return 18;
+ else
+ return 12;
}
int
}
/* { dg-final { scan-assembler-not "and\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" } } */
-/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+, lsr 4" } } */
+/* { dg-final { scan-assembler-times "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" 2 } } */