Use the pipe specific macros to access these registers.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
struct drm_crtc * crtc = dbi_output->base.base.crtc;
struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL;
u32 dpll_reg = MRST_DPLL_A;
- u32 pipeconf_reg = PIPEACONF;
- u32 dspcntr_reg = DSPACNTR;
- u32 dspbase_reg = DSPABASE;
- u32 dspsurf_reg = DSPASURF;
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ u32 dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
+ u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
PSB_DEBUG_ENTRY(" \n");
if(pipe == 2) {
dpll_reg = MRST_DPLL_A;
- pipeconf_reg = PIPECCONF;
- dspcntr_reg = DSPCCNTR;
- dspbase_reg = MDFLD_DSPCBASE;
- dspsurf_reg = DSPCSURF;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
+ dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C);
}
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL;
u32 reg_val;
u32 dpll_reg = MRST_DPLL_A;
- u32 pipeconf_reg = PIPEACONF;
- u32 dspcntr_reg = DSPACNTR;
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
/*if mode setting on-going, back off*/
if((dbi_output->mode_flags & MODE_SETTING_ON_GOING) ||
if(pipe == 2) {
dpll_reg = MRST_DPLL_A;
- pipeconf_reg = PIPECCONF;
- dspcntr_reg = DSPCCNTR;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
}
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
{
if(REG_READ(MRST_DPLL_A) & DPLL_VCO_ENABLE)
return false;
- if((REG_READ(PIPEACONF) & PIPEACONF_ENABLE) ||
- (REG_READ(PIPECCONF) & PIPEACONF_ENABLE))
+ if ((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) & PIPEACONF_ENABLE) ||
+ (REG_READ(PSB_PIPECONF(PSB_PIPE_C)) & PIPEACONF_ENABLE))
return false;
- if((REG_READ(DSPACNTR) & DISPLAY_PLANE_ENABLE) ||
- (REG_READ(DSPCCNTR) & DISPLAY_PLANE_ENABLE))
+ if ((REG_READ(PSB_DSPCNTR(PSB_PIPE_A)) & DISPLAY_PLANE_ENABLE) ||
+ (REG_READ(PSB_DSPCNTR(PSB_PIPE_C)) & DISPLAY_PLANE_ENABLE))
return false;
return true;
mdfld_plane_t plane)
{
u32 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A);
- u32 dspsize_reg = DSPASIZE;
- u32 dspoff_reg = DSPALINOFF;
- u32 dspsurf_reg = DSPASURF;
- u32 dspstride_reg = DSPASTRIDE;
+ u32 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A);
+ u32 dspoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
+ u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
+ u32 dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_A);
u32 stride;
struct psb_drm_dpu_rect * rect = &dpu_info->damage_pipea;
struct drm_device * dev = dpu_info->dev;
if(plane == MDFLD_PLANEC) {
pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C);
- dspsize_reg = DSPCSIZE;
- dspoff_reg = DSPCLINOFF;
- dspsurf_reg = DSPCSURF;
- dspstride_reg = DSPCSTRIDE;
+ dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C);
+ dspoff_reg = PSB_DSPLINOFF(PSB_PIPE_C);
+ dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C);
+ dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_C);
rect = &dpu_info->damage_pipec;
}
bool pipe_updated[2];
unsigned long irq_flags;
u32 dpll_reg = MRST_DPLL_A;
- u32 dspcntr_reg = DSPACNTR;
- u32 pipeconf_reg = PIPEACONF;
- u32 dsplinoff_reg = DSPALINOFF;
- u32 dspsurf_reg = DSPASURF;
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
+ u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
int pipe;
int i;
int ret;
pipe = dbi_output[i]->channel_num ? 2 : 0;
if(pipe == 2) {
- dspcntr_reg = DSPCCNTR;
- pipeconf_reg = PIPECCONF;
- dsplinoff_reg = DSPCLINOFF;
- dspsurf_reg = DSPCSURF;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C);
+ dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C);
}
if (!(REG_READ(MIPI_GEN_FIFO_STAT_REG(pipe)) & BIT(27)) ||
struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL;
u32 reg_val;
u32 dpll_reg = MRST_DPLL_A;
- u32 pipeconf_reg = PIPEACONF;
- u32 dspcntr_reg = DSPACNTR;
- u32 dspbase_reg = DSPABASE;
- u32 dspsurf_reg = DSPASURF;
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ u32 dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
+ u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
PSB_DEBUG_ENTRY("\n");
if(pipe == 2) {
dpll_reg = MRST_DPLL_A;
- pipeconf_reg = PIPECCONF;
- dspcntr_reg = DSPCCNTR;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
dspbase_reg = MDFLD_DSPCBASE;
- dspsurf_reg = DSPCSURF;
+ dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C);
}
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
static void dsi_set_pipe_plane_enable_state(struct drm_device *dev, int state, int pipe)
{
struct drm_psb_private *dev_priv = dev->dev_private;
- u32 pipeconf_reg = PIPEACONF;
- u32 dspcntr_reg = DSPACNTR;
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
u32 pipeconf = dev_priv->pipeconf;
u32 dspcntr = dev_priv->dspcntr;
__func__, state, pipe);
if (pipe) {
- pipeconf_reg = PIPECCONF;
- dspcntr_reg = DSPCCNTR;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
} else {
mipi &= (~0x03);
}
REG_WRITE(dspcntr_reg, dspcntr);
} else {
u32 val;
- u32 dspbase_reg = pipe ? MDFLD_DSPCBASE : MRST_DSPABASE;
+ u32 dspbase_reg = PSB_DSPBASE(pipe);
/* Put DSI lanes to ULPS to disable pipe */
REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1);
int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
struct drm_device * dev = dsi_config->dev;
struct drm_psb_private * dev_priv = dev->dev_private;
- u32 pipeconf_reg = PIPEACONF;
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
PSB_DEBUG_ENTRY("set power %s on pipe %d\n", on ? "On" : "Off", pipe);
if (pipe)
- pipeconf_reg = PIPECCONF;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
/*start up display island if it was shutdown*/
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
struct drm_psb_private * dev_priv = dev->dev_private;
int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
- u32 pipeconf_reg = PIPEACONF;
- u32 dspcntr_reg = DSPACNTR;
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
u32 pipeconf = dev_priv->pipeconf;
u32 dspcntr = dev_priv->dspcntr;
PSB_DEBUG_ENTRY("set mode %dx%d on pipe %d", mode->hdisplay, mode->vdisplay, pipe);
if(pipe) {
- pipeconf_reg = PIPECCONF;
- dspcntr_reg = DSPCCNTR;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
} else {
if (get_panel_type(dev, pipe) == TC35876X)
mipi &= (~0x03); /* Use all four lanes */
mdfld_mipi_config(dsi_config, pipe);
mdfld_set_pipe_timing(dsi_config, pipe);
- REG_WRITE(DSPABASE, 0x00);
- REG_WRITE(DSPASTRIDE, (mode->hdisplay * 4));
- REG_WRITE(DSPASIZE,
+ REG_WRITE(PSB_DSPBASE(PSB_PIPE_A), 0x00);
+ REG_WRITE(PSB_DSPSTRIDE(PSB_PIPE_A), (mode->hdisplay * 4));
+ REG_WRITE(PSB_DSPSIZE(PSB_PIPE_A),
((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
- REG_WRITE(DSPACNTR, 0x98000000);
- REG_WRITE(DSPASURF, 0x00);
+ REG_WRITE(PSB_DSPCNTR(PSB_PIPE_A), 0x98000000);
+ REG_WRITE(PSB_DSPSURF(PSB_PIPE_A), 0x00);
REG_WRITE(VGACNTRL, 0x80000000);
REG_WRITE(DEVICE_READY_REG, 0x00000001);
/*init regs*/
if(pipe == 0) {
pkg_sender->dpll_reg = MRST_DPLL_A;
- pkg_sender->dspcntr_reg = DSPACNTR;
- pkg_sender->pipeconf_reg = PIPEACONF;
- pkg_sender->dsplinoff_reg = DSPALINOFF;
- pkg_sender->dspsurf_reg = DSPASURF;
- pkg_sender->pipestat_reg = PIPEASTAT;
+ pkg_sender->dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ pkg_sender->pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ pkg_sender->dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
+ pkg_sender->dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
+ pkg_sender->pipestat_reg = PSB_PIPESTAT(PSB_PIPE_A);
} else if (pipe == 2) {
pkg_sender->dpll_reg = MRST_DPLL_A;
- pkg_sender->dspcntr_reg = DSPCCNTR;
- pkg_sender->pipeconf_reg = PIPECCONF;
- pkg_sender->dsplinoff_reg = DSPCLINOFF;
- pkg_sender->dspsurf_reg = DSPCSURF;
- pkg_sender->pipestat_reg = PIPECSTAT;
+ pkg_sender->dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ pkg_sender->pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ pkg_sender->dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C);
+ pkg_sender->dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C);
+ pkg_sender->pipestat_reg = PSB_PIPESTAT(PSB_PIPE_C);
}
pkg_sender->mipi_intr_stat_reg = MIPI_INTR_STAT_REG(pipe);
width_align = (otm_adjusted_mode.width + 31) & ~31;
pipebstride = 4 * width_align;
- REG_WRITE(DSPBSTRIDE, pipebstride);
+ REG_WRITE(PSB_DSPSTRIDE(PSB_PIPE_B), pipebstride);
fb_width = otm_adjusted_mode.width;
fb_height = otm_adjusted_mode.height;
}
guardband_reg.interrupt_status = 1;
PSB_WVDC32(guardband_reg.data, HISTOGRAM_INT_CONTROL);
- irqCtrl = PSB_RVDC32(PIPEASTAT);
- PSB_WVDC32(irqCtrl | PIPE_DPST_EVENT_ENABLE, PIPEASTAT);
+ irqCtrl = PSB_RVDC32(PSB_PIPESTAT(PSB_PIPE_A));
+ PSB_WVDC32(irqCtrl | PIPE_DPST_EVENT_ENABLE,
+ PSB_PIPESTAT(PSB_PIPE_A));
/* Wait for two vblanks */
} else {
guardband_reg.data = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
ie_hist_cont_reg.ie_histogram_enable = 0;
PSB_WVDC32(ie_hist_cont_reg.data, HISTOGRAM_LOGIC_CONTROL);
- irqCtrl = PSB_RVDC32(PIPEASTAT);
+ irqCtrl = PSB_RVDC32(PSB_PIPESTAT(PSB_PIPE_A));
irqCtrl &= ~PIPE_DPST_EVENT_ENABLE;
- PSB_WVDC32(irqCtrl, PIPEASTAT);
+ PSB_WVDC32(irqCtrl, PSB_PIPESTAT(PSB_PIPE_A));
}
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
psb_fb = to_psb_fb(drm_fb);
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
- REG_WRITE(DSPASURF, psb_fb->offset);
- REG_READ(DSPASURF);
+ REG_WRITE(PSB_DSPSURF(PSB_PIPE_A), psb_fb->offset);
+ REG_READ(PSB_DSPSURF(PSB_PIPE_A));
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
} else {
dev_priv->saveDSPASURF = psb_fb->offset;
if (arg->sprite_enable_mask != 0) {
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
PSB_WVDC32(0x1F3E, DSPARB);
- PSB_WVDC32(arg->sprite.dspa_control | PSB_RVDC32(DSPACNTR), DSPACNTR);
+ PSB_WVDC32(arg->sprite.dspa_control |
+ PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_A)),
+ PSB_DSPCNTR(PSB_PIPE_A));
PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
- PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
- PSB_RVDC32(DSPASURF);
- PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
- PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
- PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
- PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
- PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
- PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
- PSB_RVDC32(DSPCSURF);
+ PSB_WVDC32(PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A)),
+ PSB_DSPSURF(PSB_PIPE_A));
+ PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A));
+ PSB_WVDC32(arg->sprite.dspc_control,
+ PSB_DSPCNTR(PSB_PIPE_C));
+ PSB_WVDC32(arg->sprite.dspc_stride,
+ PSB_DSPSTRIDE(PSB_PIPE_C));
+ PSB_WVDC32(arg->sprite.dspc_position,
+ PSB_DSPPOS(PSB_PIPE_C));
+ PSB_WVDC32(arg->sprite.dspc_linear_offset,
+ PSB_DSPLINOFF(PSB_PIPE_C));
+ PSB_WVDC32(arg->sprite.dspc_size,
+ PSB_DSPSIZE(PSB_PIPE_C));
+ PSB_WVDC32(arg->sprite.dspc_surface,
+ PSB_DSPSURF(PSB_PIPE_C));
+ PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C));
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
}
if (arg->sprite_disable_mask != 0) {
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
PSB_WVDC32(0x3F3E, DSPARB);
- PSB_WVDC32(0x0, DSPCCNTR);
- PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
- PSB_RVDC32(DSPCSURF);
+ PSB_WVDC32(0x0, PSB_DSPCNTR(PSB_PIPE_C));
+ PSB_WVDC32(arg->sprite.dspc_surface,
+ PSB_DSPSURF(PSB_PIPE_C));
+ PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C));
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
}
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
uint32_t temp;
if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
- temp = PSB_RVDC32(DSPACNTR);
+ temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_A));
temp &= ~DISPPLANE_PIXFORMAT_MASK;
temp &= ~DISPPLANE_BOTTOM;
temp |= DISPPLANE_32BPP;
- PSB_WVDC32(temp, DSPACNTR);
-
- temp = PSB_RVDC32(DSPABASE);
- PSB_WVDC32(temp, DSPABASE);
- PSB_RVDC32(DSPABASE);
- temp = PSB_RVDC32(DSPASURF);
- PSB_WVDC32(temp, DSPASURF);
- PSB_RVDC32(DSPASURF);
+ PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_A));
+
+ temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_A));
+ PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_A));
+ PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_A));
+ temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A));
+ PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_A));
+ PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A));
}
if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
- temp = PSB_RVDC32(DSPBCNTR);
+ temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_B));
temp &= ~DISPPLANE_PIXFORMAT_MASK;
temp &= ~DISPPLANE_BOTTOM;
temp |= DISPPLANE_32BPP;
- PSB_WVDC32(temp, DSPBCNTR);
-
- temp = PSB_RVDC32(DSPBBASE);
- PSB_WVDC32(temp, DSPBBASE);
- PSB_RVDC32(DSPBBASE);
- temp = PSB_RVDC32(DSPBSURF);
- PSB_WVDC32(temp, DSPBSURF);
- PSB_RVDC32(DSPBSURF);
+ PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_B));
+
+ temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_B));
+ PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_B));
+ PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_B));
+ temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_B));
+ PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_B));
+ PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_B));
}
if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
- temp = PSB_RVDC32(DSPCCNTR);
+ temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_C));
temp &= ~DISPPLANE_PIXFORMAT_MASK;
temp &= ~DISPPLANE_BOTTOM;
temp |= DISPPLANE_32BPP;
- PSB_WVDC32(temp, DSPCCNTR);
-
- temp = PSB_RVDC32(DSPCBASE);
- PSB_WVDC32(temp, DSPCBASE);
- PSB_RVDC32(DSPCBASE);
- temp = PSB_RVDC32(DSPCSURF);
- PSB_WVDC32(temp, DSPCSURF);
- PSB_RVDC32(DSPCSURF);
+ PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_C));
+
+ temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_C));
+ PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_C));
+ PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_C));
+ temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C));
+ PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_C));
+ PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C));
}
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
uint32_t temp;
if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
- temp = PSB_RVDC32(DSPACNTR);
+ temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_A));
temp &= ~DISPPLANE_PIXFORMAT_MASK;
temp |= DISPPLANE_32BPP_NO_ALPHA;
- PSB_WVDC32(temp, DSPACNTR);
-
- temp = PSB_RVDC32(DSPABASE);
- PSB_WVDC32(temp, DSPABASE);
- PSB_RVDC32(DSPABASE);
- temp = PSB_RVDC32(DSPASURF);
- PSB_WVDC32(temp, DSPASURF);
- PSB_RVDC32(DSPASURF);
+ PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_A));
+
+ temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_A));
+ PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_A));
+ PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_A));
+ temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A));
+ PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_A));
+ PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A));
}
if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
- temp = PSB_RVDC32(DSPBCNTR);
+ temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_B));
temp &= ~DISPPLANE_PIXFORMAT_MASK;
temp |= DISPPLANE_32BPP_NO_ALPHA;
- PSB_WVDC32(temp, DSPBCNTR);
-
- temp = PSB_RVDC32(DSPBBASE);
- PSB_WVDC32(temp, DSPBBASE);
- PSB_RVDC32(DSPBBASE);
- temp = PSB_RVDC32(DSPBSURF);
- PSB_WVDC32(temp, DSPBSURF);
- PSB_RVDC32(DSPBSURF);
+ PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_B));
+
+ temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_B));
+ PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_B));
+ PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_B));
+ temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_B));
+ PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_B));
+ PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_B));
}
if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
- temp = PSB_RVDC32(DSPCCNTR);
+ temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_C));
temp &= ~DISPPLANE_PIXFORMAT_MASK;
temp |= DISPPLANE_32BPP_NO_ALPHA;
- PSB_WVDC32(temp, DSPCCNTR);
-
- temp = PSB_RVDC32(DSPCBASE);
- PSB_WVDC32(temp, DSPCBASE);
- PSB_RVDC32(DSPCBASE);
- temp = PSB_RVDC32(DSPCSURF);
- PSB_WVDC32(temp, DSPCSURF);
- PSB_RVDC32(DSPCSURF);
+ PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_C));
+
+ temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_C));
+ PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_C));
+ PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_C));
+ temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C));
+ PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_C));
+ PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C));
}
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
return;
}
- crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR);
- crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF);
+ crtc_state->saveDSPCNTR = REG_READ(PSB_DSPCNTR(pipe));
+ crtc_state->savePIPECONF = REG_READ(PSB_PIPECONF(pipe));
crtc_state->savePIPESRC = REG_READ(PSB_PIPESRC(pipe));
crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);
crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);
crtc_state->saveVTOTAL = REG_READ(PSB_VTOTAL(pipe));
crtc_state->saveVBLANK = REG_READ(PSB_VBLANK(pipe));
crtc_state->saveVSYNC = REG_READ(PSB_VSYNC(pipe));
- crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE);
+ crtc_state->saveDSPSTRIDE = REG_READ(PSB_DSPSTRIDE(pipe));
/*NOTE: DSPSIZE DSPPOS only for psb*/
- crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE);
- crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS);
+ crtc_state->saveDSPSIZE = REG_READ(PSB_DSPSIZE(pipe));
+ crtc_state->saveDSPPOS = REG_READ(PSB_DSPPOS(pipe));
- crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE);
+ crtc_state->saveDSPBASE = REG_READ(PSB_DSPBASE(pipe));
DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
crtc_state->saveDSPCNTR,
DRM_DEBUG(
"current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
- REG_READ(pipeA ? DSPACNTR : DSPBCNTR),
- REG_READ(pipeA ? PIPEACONF : PIPEBCONF),
+ REG_READ(PSB_DSPCNTR(pipe)),
+ REG_READ(PSB_PIPECONF(pipe)),
REG_READ(PSB_PIPESRC(pipe)),
REG_READ(pipeA ? FPA0 : FPB0),
REG_READ(pipeA ? FPA1 : FPB1),
REG_READ(PSB_VTOTAL(pipe)),
REG_READ(PSB_VBLANK(pipe)),
REG_READ(PSB_VSYNC(pipe)),
- REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE),
- REG_READ(pipeA ? DSPASIZE : DSPBSIZE),
- REG_READ(pipeA ? DSPAPOS : DSPBPOS),
- REG_READ(pipeA ? DSPABASE : DSPBBASE)
+ REG_READ(PSB_DSPSTRIDE(pipe)),
+ REG_READ(PSB_DSPSIZE(pipe)),
+ REG_READ(PSB_DSPPOS(pipe)),
+ REG_READ(PSB_DSPBASE(pipe))
);
DRM_DEBUG(
REG_WRITE(PSB_VTOTAL(pipe), crtc_state->saveVTOTAL);
REG_WRITE(PSB_VBLANK(pipe), crtc_state->saveVBLANK);
REG_WRITE(PSB_VSYNC(pipe), crtc_state->saveVSYNC);
- REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE);
+ REG_WRITE(PSB_DSPSTRIDE(pipe), crtc_state->saveDSPSTRIDE);
- REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE);
- REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS);
+ REG_WRITE(PSB_DSPSIZE(pipe), crtc_state->saveDSPSIZE);
+ REG_WRITE(PSB_DSPPOS(pipe), crtc_state->saveDSPPOS);
REG_WRITE(PSB_PIPESRC(pipe), crtc_state->savePIPESRC);
- REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
- REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF);
+ REG_WRITE(PSB_DSPBASE(pipe), crtc_state->saveDSPBASE);
+ REG_WRITE(PSB_PIPECONF(pipe), crtc_state->savePIPECONF);
psb_intel_wait_for_vblank(dev);
- REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR);
- REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
+ REG_WRITE(PSB_DSPCNTR(pipe), crtc_state->saveDSPCNTR);
+ REG_WRITE(PSB_DSPBASE(pipe), crtc_state->saveDSPBASE);
psb_intel_wait_for_vblank(dev);
void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)
{
int count, temp;
- u32 pipeconf_reg = PIPEACONF;
-
- switch (pipe) {
- case 0:
- break;
- case 1:
- pipeconf_reg = PIPEBCONF;
- break;
- case 2:
- pipeconf_reg = PIPECCONF;
- break;
- default:
- DRM_ERROR("Illegal Pipe Number. \n");
- return;
- }
+ u32 pipeconf_reg = PSB_PIPECONF(pipe);
/* FIXME JLIU7_PO */
psb_intel_wait_for_vblank(dev);
void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe)
{
int count, temp;
- u32 pipeconf_reg = PIPEACONF;
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
switch (pipe) {
case 0:
break;
case 1:
- pipeconf_reg = PIPEBCONF;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
break;
case 2:
- pipeconf_reg = PIPECCONF;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
break;
default:
DRM_ERROR("Illegal Pipe Number. \n");
void mdfld__intel_plane_set_alpha(int enable)
{
struct drm_device *dev = &globle_dev;
- int dspcntr_reg = DSPACNTR;
+ int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
u32 dspcntr;
dspcntr = REG_READ(dspcntr_reg);
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
int pipe = psb_intel_crtc->pipe;
unsigned long Start, Offset;
- int dsplinoff = DSPALINOFF;
- int dspsurf = DSPASURF;
- int dspstride = DSPASTRIDE;
- int dspcntr_reg = DSPACNTR;
+ int dsplinoff = PSB_DSPLINOFF(PSB_PIPE_A);
+ int dspsurf = PSB_DSPSURF(PSB_PIPE_A);
+ int dspstride = PSB_DSPSTRIDE(PSB_PIPE_A);
+ int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
u32 dspcntr;
int ret;
switch (pipe) {
case 0:
- dsplinoff = DSPALINOFF;
+ dsplinoff = PSB_DSPLINOFF(PSB_PIPE_A);
break;
case 1:
- dsplinoff = DSPBLINOFF;
- dspsurf = DSPBSURF;
- dspstride = DSPBSTRIDE;
- dspcntr_reg = DSPBCNTR;
+ dsplinoff = PSB_DSPLINOFF(PSB_PIPE_B);
+ dspsurf = PSB_DSPSURF(PSB_PIPE_B);
+ dspstride = PSB_DSPSTRIDE(PSB_PIPE_B);
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
break;
case 2:
- dsplinoff = DSPCLINOFF;
- dspsurf = DSPCSURF;
- dspstride = DSPCSTRIDE;
- dspcntr_reg = DSPCCNTR;
+ dsplinoff = PSB_DSPLINOFF(PSB_PIPE_C);
+ dspsurf = PSB_DSPSURF(PSB_PIPE_C);
+ dspstride = PSB_DSPSTRIDE(PSB_PIPE_C);
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
break;
default:
DRM_ERROR("Illegal Pipe Number. \n");
void mdfld_disable_crtc (struct drm_device *dev, int pipe)
{
int dpll_reg = MRST_DPLL_A;
- int dspcntr_reg = DSPACNTR;
- int dspbase_reg = MRST_DSPABASE;
- int pipeconf_reg = PIPEACONF;
+ int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
+ int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
u32 temp;
PSB_DEBUG_ENTRY("pipe = %d \n", pipe);
break;
case 1:
dpll_reg = MDFLD_DPLL_B;
- dspcntr_reg = DSPBCNTR;
- dspbase_reg = DSPBSURF;
- pipeconf_reg = PIPEBCONF;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
+ dspbase_reg = PSB_DSPSURF(PSB_PIPE_B);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
break;
case 2:
dpll_reg = MRST_DPLL_A;
- dspcntr_reg = DSPCCNTR;
- dspbase_reg = MDFLD_DSPCBASE;
- pipeconf_reg = PIPECCONF;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
break;
default:
DRM_ERROR("Illegal Pipe Number. \n");
temp = REG_READ(dpll_reg);
if (temp & DPLL_VCO_ENABLE) {
- if (((pipe != 1) && !((REG_READ(PIPEACONF) | REG_READ(PIPECCONF)) & PIPEACONF_ENABLE))
+ if (((pipe != 1) &&
+ !((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) |
+ REG_READ(PSB_PIPECONF(PSB_PIPE_C))) & PIPEACONF_ENABLE))
|| (pipe == 1)){
temp &= ~(DPLL_VCO_ENABLE);
REG_WRITE(dpll_reg, temp);
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
int pipe = psb_intel_crtc->pipe;
int dpll_reg = MRST_DPLL_A;
- int dspcntr_reg = DSPACNTR;
- int dspbase_reg = MRST_DSPABASE;
- int pipeconf_reg = PIPEACONF;
- u32 pipestat_reg = PIPEASTAT;
+ int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
+ int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ u32 pipestat_reg = PSB_PIPESTAT(PSB_PIPE_A);
u32 pipeconf = dev_priv->pipeconf;
u32 dspcntr = dev_priv->dspcntr;
u32 temp;
break;
case 1:
dpll_reg = DPLL_B;
- dspcntr_reg = DSPBCNTR;
- dspbase_reg = MRST_DSPBBASE;
- pipeconf_reg = PIPEBCONF;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
+ dspbase_reg = PSB_DSPBASE(PSB_PIPE_B);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
pipeconf = dev_priv->pipeconf1;
dspcntr = dev_priv->dspcntr1;
dpll_reg = MDFLD_DPLL_B;
break;
case 2:
dpll_reg = MRST_DPLL_A;
- dspcntr_reg = DSPCCNTR;
- dspbase_reg = MDFLD_DSPCBASE;
- pipeconf_reg = PIPECCONF;
- pipestat_reg = PIPECSTAT;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ pipestat_reg = PSB_PIPESTAT(PSB_PIPE_C);
pipeconf = dev_priv->pipeconf2;
dspcntr = dev_priv->dspcntr2;
break;
temp = REG_READ(dpll_reg);
if (temp & DPLL_VCO_ENABLE) {
- if (((pipe != 1) && !((REG_READ(PIPEACONF) | REG_READ(PIPECCONF)) & PIPEACONF_ENABLE))
- || (pipe == 1)){
+ if (((pipe != 1) &&
+ !((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) |
+ REG_READ(PSB_PIPECONF(PSB_PIPE_C))) &
+ PIPEACONF_ENABLE)) ||
+ (pipe == 1)) {
temp &= ~(DPLL_VCO_ENABLE);
REG_WRITE(dpll_reg, temp);
REG_READ(dpll_reg);
int pipe = psb_intel_crtc->pipe;
int fp_reg = MRST_FPA0;
int dpll_reg = MRST_DPLL_A;
- int dspcntr_reg = DSPACNTR;
- int pipeconf_reg = PIPEACONF;
+ int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
int htot_reg = PSB_HTOTAL(PSB_PIPE_A);
int hblank_reg = PSB_HBLANK(PSB_PIPE_A);
int hsync_reg = PSB_HSYNC(PSB_PIPE_A);
int vtot_reg = PSB_VTOTAL(PSB_PIPE_A);
int vblank_reg = PSB_VBLANK(PSB_PIPE_A);
int vsync_reg = PSB_VSYNC(PSB_PIPE_A);
- int dspsize_reg = DSPASIZE;
- int dsppos_reg = DSPAPOS;
+ int dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A);
+ int dsppos_reg = PSB_DSPPOS(PSB_PIPE_A);
int pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A);
u32 *pipeconf = &dev_priv->pipeconf;
u32 *dspcntr = &dev_priv->dspcntr;
case 1:
fp_reg = FPB0;
dpll_reg = DPLL_B;
- dspcntr_reg = DSPBCNTR;
- pipeconf_reg = PIPEBCONF;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
htot_reg = PSB_HTOTAL(PSB_PIPE_B);
hblank_reg = PSB_HBLANK(PSB_PIPE_B);
hsync_reg = PSB_HSYNC(PSB_PIPE_B);
vtot_reg = PSB_VTOTAL(PSB_PIPE_B);
vblank_reg = PSB_VBLANK(PSB_PIPE_B);
vsync_reg = PSB_VSYNC(PSB_PIPE_B);
- dspsize_reg = DSPBSIZE;
- dsppos_reg = DSPBPOS;
+ dspsize_reg = PSB_DSPSIZE(PSB_PIPE_B);
+ dsppos_reg = PSB_DSPPOS(PSB_PIPE_B);
pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B);
pipeconf = &dev_priv->pipeconf1;
dspcntr = &dev_priv->dspcntr1;
break;
case 2:
dpll_reg = MRST_DPLL_A;
- dspcntr_reg = DSPCCNTR;
- pipeconf_reg = PIPECCONF;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
htot_reg = PSB_HTOTAL(PSB_PIPE_C);
hblank_reg = PSB_HBLANK(PSB_PIPE_C);
hsync_reg = PSB_HSYNC(PSB_PIPE_C);
vtot_reg = PSB_VTOTAL(PSB_PIPE_C);
vblank_reg = PSB_VBLANK(PSB_PIPE_C);
vsync_reg = PSB_VSYNC(PSB_PIPE_C);
- dspsize_reg = DSPCSIZE;
- dsppos_reg = DSPCPOS;
+ dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C);
+ dsppos_reg = PSB_DSPPOS(PSB_PIPE_C);
pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C);
pipeconf = &dev_priv->pipeconf2;
dspcntr = &dev_priv->dspcntr2;
static inline u32
psb_pipestat(int pipe)
{
- if (pipe == 0)
- return PIPEASTAT;
- if (pipe == 1)
- return PIPEBSTAT;
- if (pipe == 2)
- return PIPECSTAT;
- BUG();
+ return PSB_PIPESTAT(pipe);
}
static inline u32
static inline u32
mid_pipeconf(int pipe)
{
- if (pipe == 0)
- return PIPEACONF;
- if (pipe == 1)
- return PIPEBCONF;
- if (pipe == 2)
- return PIPECCONF;
- BUG();
+ return PSB_PIPECONF(pipe);
}
static void trcmd_vblank_power(unsigned type, int pipe)
ie_hist_cont_reg.ie_histogram_enable = 0;
PSB_WVDC32(ie_hist_cont_reg.data, HISTOGRAM_LOGIC_CONTROL);
- irqCtrl = PSB_RVDC32(PIPEASTAT);
+ irqCtrl = PSB_RVDC32(PSB_PIPESTAT(PSB_PIPE_A));
irqCtrl &= ~PIPE_DPST_EVENT_ENABLE;
- PSB_WVDC32(irqCtrl, PIPEASTAT);
+ PSB_WVDC32(irqCtrl, PSB_PIPESTAT(PSB_PIPE_A));
}
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
if ((pwm_reg & PWM_PHASEIN_INT_ENABLE) &&
*/
u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
{
- uint32_t high_frame = PIPEAFRAMEHIGH;
- uint32_t low_frame = PIPEAFRAMEPIXEL;
- uint32_t pipeconf_reg = PIPEACONF;
+ uint32_t high_frame = PSB_PIPEFRAMEHIGH(PSB_PIPE_A);
+ uint32_t low_frame = PSB_PIPEFRAMEPIXEL(PSB_PIPE_A);
+ uint32_t pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
uint32_t reg_val = 0;
uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
case 0:
break;
case 1:
- high_frame = PIPEBFRAMEHIGH;
- low_frame = PIPEBFRAMEPIXEL;
- pipeconf_reg = PIPEBCONF;
+ high_frame = PSB_PIPEFRAMEHIGH(PSB_PIPE_B);
+ low_frame = PSB_PIPEFRAMEPIXEL(PSB_PIPE_B);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
break;
case 2:
- high_frame = PIPECFRAMEHIGH;
- low_frame = PIPECFRAMEPIXEL;
- pipeconf_reg = PIPECCONF;
+ high_frame = PSB_PIPEFRAMEHIGH(PSB_PIPE_C);
+ low_frame = PSB_PIPEFRAMEPIXEL(PSB_PIPE_C);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
break;
default:
DRM_ERROR("%s, invalded pipe. \n", __FUNCTION__);
u32 reg_val = 0, mask = 0;
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
- reg_val = REG_READ(PIPEBCONF);
+ reg_val = REG_READ(PSB_PIPECONF(PSB_PIPE_B));
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
/* regester */
u32 dpll_reg = MRST_DPLL_A;
u32 fp_reg = MRST_FPA0;
- u32 pipeconf_reg = PIPEACONF;
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
u32 htot_reg = PSB_HTOTAL(PSB_PIPE_A);
u32 hblank_reg = PSB_HBLANK(PSB_PIPE_A);
u32 hsync_reg = PSB_HSYNC(PSB_PIPE_A);
u32 vblank_reg = PSB_VBLANK(PSB_PIPE_A);
u32 vsync_reg = PSB_VSYNC(PSB_PIPE_A);
u32 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A);
- u32 dspstride_reg = DSPASTRIDE;
- u32 dsplinoff_reg = DSPALINOFF;
- u32 dsptileoff_reg = DSPATILEOFF;
- u32 dspsize_reg = DSPASIZE;
- u32 dsppos_reg = DSPAPOS;
- u32 dspsurf_reg = DSPASURF;
+ u32 dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_A);
+ u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
+ u32 dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_A);
+ u32 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A);
+ u32 dsppos_reg = PSB_DSPPOS(PSB_PIPE_A);
+ u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
u32 mipi_reg = MIPI;
- u32 dspcntr_reg = DSPACNTR;
- u32 dspstatus_reg = PIPEASTAT;
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ u32 dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_A);
u32 palette_reg = PALETTE_A;
/* pointer to values */
/* regester */
dpll_reg = MDFLD_DPLL_B;
fp_reg = MDFLD_DPLL_DIV0;
- pipeconf_reg = PIPEBCONF;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
htot_reg = PSB_HTOTAL(PSB_PIPE_B);
hblank_reg = PSB_HBLANK(PSB_PIPE_B);
hsync_reg = PSB_HSYNC(PSB_PIPE_B);
vblank_reg = PSB_VBLANK(PSB_PIPE_B);
vsync_reg = PSB_VSYNC(PSB_PIPE_B);
pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B);
- dspstride_reg = DSPBSTRIDE;
- dsplinoff_reg = DSPBLINOFF;
- dsptileoff_reg = DSPBTILEOFF;
- dspsize_reg = DSPBSIZE;
- dsppos_reg = DSPBPOS;
- dspsurf_reg = DSPBSURF;
- dspcntr_reg = DSPBCNTR;
- dspstatus_reg = PIPEBSTAT;
+ dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_B);
+ dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_B);
+ dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_B);
+ dspsize_reg = PSB_DSPSIZE(PSB_PIPE_B);
+ dsppos_reg = PSB_DSPPOS(PSB_PIPE_B);
+ dspsurf_reg = PSB_DSPSURF(PSB_PIPE_B);
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
+ dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_B);
palette_reg = PALETTE_B;
/* values */
break;
case 2:
/* regester */
- pipeconf_reg = PIPECCONF;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
htot_reg = PSB_HTOTAL(PSB_PIPE_C);
hblank_reg = PSB_HBLANK(PSB_PIPE_C);
hsync_reg = PSB_HSYNC(PSB_PIPE_C);
vblank_reg = PSB_VBLANK(PSB_PIPE_C);
vsync_reg = PSB_VSYNC(PSB_PIPE_C);
pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C);
- dspstride_reg = DSPCSTRIDE;
- dsplinoff_reg = DSPCLINOFF;
- dsptileoff_reg = DSPCTILEOFF;
- dspsize_reg = DSPCSIZE;
- dsppos_reg = DSPCPOS;
- dspsurf_reg = DSPCSURF;
+ dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_C);
+ dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C);
+ dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_C);
+ dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C);
+ dsppos_reg = PSB_DSPPOS(PSB_PIPE_C);
+ dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C);
mipi_reg = MIPI_C;
- dspcntr_reg = DSPCCNTR;
- dspstatus_reg = PIPECSTAT;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_C);
palette_reg = PALETTE_C;
/* pointer to values */
/* regester */
u32 dpll_reg = MRST_DPLL_A;
u32 fp_reg = MRST_FPA0;
- u32 pipeconf_reg = PIPEACONF;
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
u32 htot_reg = PSB_HTOTAL(PSB_PIPE_A);
u32 hblank_reg = PSB_HBLANK(PSB_PIPE_A);
u32 hsync_reg = PSB_HSYNC(PSB_PIPE_A);
u32 vblank_reg = PSB_VBLANK(PSB_PIPE_A);
u32 vsync_reg = PSB_VSYNC(PSB_PIPE_A);
u32 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A);
- u32 dspstride_reg = DSPASTRIDE;
- u32 dsplinoff_reg = DSPALINOFF;
- u32 dsptileoff_reg = DSPATILEOFF;
- u32 dspsize_reg = DSPASIZE;
- u32 dsppos_reg = DSPAPOS;
- u32 dspsurf_reg = DSPASURF;
- u32 dspstatus_reg = PIPEASTAT;
+ u32 dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_A);
+ u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
+ u32 dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_A);
+ u32 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A);
+ u32 dsppos_reg = PSB_DSPPOS(PSB_PIPE_A);
+ u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
+ u32 dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_A);
u32 mipi_reg = MIPI;
- u32 dspcntr_reg = DSPACNTR;
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
u32 palette_reg = PALETTE_A;
/* values */
/* regester */
dpll_reg = MDFLD_DPLL_B;
fp_reg = MDFLD_DPLL_DIV0;
- pipeconf_reg = PIPEBCONF;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
htot_reg = PSB_HTOTAL(PSB_PIPE_B);
hblank_reg = PSB_HBLANK(PSB_PIPE_B);
hsync_reg = PSB_HSYNC(PSB_PIPE_B);
vblank_reg = PSB_VBLANK(PSB_PIPE_B);
vsync_reg = PSB_VSYNC(PSB_PIPE_B);
pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B);
- dspstride_reg = DSPBSTRIDE;
- dsplinoff_reg = DSPBLINOFF;
- dsptileoff_reg = DSPBTILEOFF;
- dspsize_reg = DSPBSIZE;
- dsppos_reg = DSPBPOS;
- dspsurf_reg = DSPBSURF;
- dspcntr_reg = DSPBCNTR;
- dspstatus_reg = PIPEBSTAT;
+ dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_B);
+ dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_B);
+ dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_B);
+ dspsize_reg = PSB_DSPSIZE(PSB_PIPE_B);
+ dsppos_reg = PSB_DSPPOS(PSB_PIPE_B);
+ dspsurf_reg = PSB_DSPSURF(PSB_PIPE_B);
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
+ dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_B);
palette_reg = PALETTE_B;
/* values */
dsi_output = dev_priv->dbi_output2;
/* regester */
- pipeconf_reg = PIPECCONF;
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
htot_reg = PSB_HTOTAL(PSB_PIPE_C);
hblank_reg = PSB_HBLANK(PSB_PIPE_C);
hsync_reg = PSB_HSYNC(PSB_PIPE_C);
vblank_reg = PSB_VBLANK(PSB_PIPE_C);
vsync_reg = PSB_VSYNC(PSB_PIPE_C);
pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C);
- dspstride_reg = DSPCSTRIDE;
- dsplinoff_reg = DSPCLINOFF;
- dsptileoff_reg = DSPCTILEOFF;
- dspsize_reg = DSPCSIZE;
- dsppos_reg = DSPCPOS;
- dspsurf_reg = DSPCSURF;
+ dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_C);
+ dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C);
+ dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_C);
+ dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C);
+ dsppos_reg = PSB_DSPPOS(PSB_PIPE_C);
+ dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C);
mipi_reg = MIPI_C;
- dspcntr_reg = DSPCCNTR;
- dspstatus_reg = PIPECSTAT;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_C);
palette_reg = PALETTE_C;
/* values */
int pipe = dsi_connector->pipe;
/*regs*/
- u32 dspcntr_reg = DSPACNTR;
- u32 pipeconf_reg = PIPEACONF;
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
/*values*/
u32 dspcntr_val = dev_priv->dspcntr;
PSB_DEBUG_ENTRY("h %d v %d\n", mode->hdisplay, mode->vdisplay);
if(pipe == 2) {
- dspcntr_reg = DSPCCNTR;
- pipeconf_reg = PIPECCONF;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
dspcntr_val = dev_priv->dspcntr2;
pipeconf_val = dev_priv->pipeconf2;
} else {
struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL;
u32 dpll_reg = MRST_DPLL_A;
- u32 dspcntr_reg = DSPACNTR;
- u32 pipeconf_reg = PIPEACONF;
- u32 dsplinoff_reg = DSPALINOFF;
- u32 dspsurf_reg = DSPASURF;
+ u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
+ u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
+ u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
/*if mode setting on-going, back off*/
if((dbi_output->mode_flags & MODE_SETTING_ON_GOING) ||
return;
if(pipe == 2) {
- dspcntr_reg = DSPCCNTR;
- pipeconf_reg = PIPECCONF;
- dsplinoff_reg = DSPCLINOFF;
- dspsurf_reg = DSPCSURF;
+ dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
+ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C);
+ dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C);
}
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
projects / kernel / kernel-mfld-blackbay.git / commitdiff