clk: renesas: r9a07g043: Add clock and reset entries for CANFD

Add clock and reset entries for CANFD in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index ea826f0..59d5405 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -100,6 +100,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
                CLK_DIVIDER_HIWORD_MASK),
        DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
                dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+       DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
        DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
                DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
        DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
@@ -198,6 +199,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
                                0x588, 0),
        DEF_MOD("sci1",         R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
                                0x588, 1),
+       DEF_MOD("canfd",        R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
+                               0x594, 0),
        DEF_MOD("gpio",         R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
                                0x598, 0),
 };
@@ -231,6 +234,8 @@ static struct rzg2l_reset r9a07g043_resets[] = {
        DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
        DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
        DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
+       DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
+       DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
        DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
        DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
        DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),