GlobalISel: mark pointer stores as legal on AArch64.

llvm-svn: 281448

diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
index 8a0b5b0..a3b52ff 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
@@ -70,7 +70,7 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
   setAction({G_FREM, s64}, Libcall);
 
   for (auto MemOp : {G_LOAD, G_STORE}) {
-    for (auto Ty : {s8, s16, s32, s64})
+    for (auto Ty : {s8, s16, s32, s64, p0})
       setAction({MemOp, Ty}, Legal);
 
     setAction({MemOp, s1}, WidenScalar);

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index bd7bbca..9b34305 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -22,6 +22,7 @@ registers:
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
+  - { id: 6, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
@@ -43,6 +44,9 @@ body: |
 
     ; CHECK: %5(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
     %5(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
+
+    ; CHECK: %6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+    %6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
 ...
 
 ---
@@ -81,4 +85,7 @@ body: |
     ; CHECK: G_STORE %5(s64), %0(p0) :: (store 8 into %ir.addr)
     %5(s64) = G_PTRTOINT %0(p0)
     G_STORE %5, %0 :: (store 8 into %ir.addr)
+
+    ; CHECK: G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
+    G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
 ...