net: hns3: Set tx ring' tc info when netdev is up

The HNS3_RING_TX_RING_TC_REG register is used to map tx ring to
specific tc, the tx queue to tc mapping is needed by the hardware
to do the correct tx schedule.

Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index b7b9ee3..b28c7e1 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -2974,6 +2974,28 @@ static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
        }
 }
 
+static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
+{
+       struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
+       int i;
+
+       for (i = 0; i < HNAE3_MAX_TC; i++) {
+               struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
+               int j;
+
+               if (!tc_info->enable)
+                       continue;
+
+               for (j = 0; j < tc_info->tqp_count; j++) {
+                       struct hnae3_queue *q;
+
+                       q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
+                       hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
+                                      tc_info->tc);
+               }
+       }
+}
+
 int hns3_init_all_ring(struct hns3_nic_priv *priv)
 {
        struct hnae3_handle *h = priv->ae_handle;
@@ -3385,6 +3407,8 @@ int hns3_nic_reset_all_ring(struct hnae3_handle *h)
                rx_ring->next_to_use = 0;
        }
 
+       hns3_init_tx_ring_tc(priv);
+
        return 0;
 }
 

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
index 0f071a0..a02a96a 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
@@ -37,6 +37,7 @@ enum hns3_nic_state {
 #define HNS3_RING_TX_RING_BASEADDR_L_REG       0x00040
 #define HNS3_RING_TX_RING_BASEADDR_H_REG       0x00044
 #define HNS3_RING_TX_RING_BD_NUM_REG           0x00048
+#define HNS3_RING_TX_RING_TC_REG               0x00050
 #define HNS3_RING_TX_RING_TAIL_REG             0x00058
 #define HNS3_RING_TX_RING_HEAD_REG             0x0005C
 #define HNS3_RING_TX_RING_FBDNUM_REG           0x00060