Merge branch 'socfpga/hw' into next/soc

From Dinh Nguyen, this is a series of patches introducing support for
socfpga hardware (Altera Cyclone5). It also includes a cleanup that
moves some of the ARMv7 cache maintenance functions to a common location,
since three other platforms aready implemented it separately.

* socfpga/hw:
  arm: socfpga: Add SMP support for actual socfpga harware
  arm: Add v7_invalidate_l1 to cache-v7.S
  arm: socfpga: Add entries to enable make dtbs socfpga
  arm: socfpga: Add new device tree source for actual socfpga HW

Trivial conflict in arch/arm/mach-tegra/headsmp.S.

Signed-off-by: Olof Johansson <olof@lixom.net>

diff --cc arch/arm/boot/dts/Makefile
Simple merge

diff --cc arch/arm/mach-socfpga/platsmp.c
Simple merge

diff --cc arch/arm/mach-socfpga/socfpga.c
Simple merge

diff --cc arch/arm/mach-tegra/headsmp.S
index b283481,fb082c4..fd473f2
--- 1/arch/arm/mach-tegra/headsmp.S
--- 2/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@@ -1,53 -1,24 +1,10 @@@
  #include <linux/linkage.h>
  #include <linux/init.h>
  
 -#include <asm/cache.h>
 -#include <asm/asm-offsets.h>
 -#include <asm/hardware/cache-l2x0.h>
 -
 -#include "flowctrl.h"
 -#include "iomap.h"
 -#include "reset.h"
  #include "sleep.h"
  
 -#define APB_MISC_GP_HIDREV    0x804
 -#define PMC_SCRATCH41 0x140
 -
 -#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
 -
          .section ".text.head", "ax"
 -      __CPUINIT
 -
  
- /*
-  * Tegra specific entry point for secondary CPUs.
-  *   The secondary kernel init calls v7_flush_dcache_all before it enables
-  *   the L1; however, the L1 comes out of reset in an undefined state, so
-  *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch
-  *   of cache lines with uninitialized data and uninitialized tags to get
-  *   written out to memory, which does really unpleasant things to the main
-  *   processor.  We fix this by performing an invalidate, rather than a
-  *   clean + invalidate, before jumping into the kernel.
-  */
- ENTRY(v7_invalidate_l1)
-         mov     r0, #0
-         mcr     p15, 2, r0, c0, c0, 0
-         mrc     p15, 1, r0, c0, c0, 0
- 
-         ldr     r1, =0x7fff
-         and     r2, r1, r0, lsr #13
- 
-         ldr     r1, =0x3ff
- 
-         and     r3, r1, r0, lsr #3  @ NumWays - 1
-         add     r2, r2, #1          @ NumSets
- 
-         and     r0, r0, #0x7
-         add     r0, r0, #4          @ SetShift
- 
-         clz     r1, r3              @ WayShift
-         add     r4, r3, #1          @ NumWays
- 1:      sub     r2, r2, #1          @ NumSets--
-         mov     r3, r4              @ Temp = NumWays
- 2:      subs    r3, r3, #1          @ Temp--
-         mov     r5, r3, lsl r1
-         mov     r6, r2, lsl r0
-         orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-         mcr     p15, 0, r5, c7, c6, 2
-         bgt     2b
-         cmp     r2, #0
-         bgt     1b
-         dsb
-         isb
-         mov     pc, lr
- ENDPROC(v7_invalidate_l1)
- 
  ENTRY(tegra_secondary_startup)
          bl      v7_invalidate_l1
        /* Enable coresight */