drm/amd/display: Use correct DTO_SRC_SEL for 128b/132b encoding

[WHY]
DP DTO isn't used for 128b/132b encoding

[HOW]
Check current link rate to determine whether using 8b/10b or 128/132b encoding

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index dfc74aea2852a36cf11e46572f78d5ba86b3a321..48dad093ae8ba845a7dbdaecdf1b1b308bd6b0a7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -7064,6 +7064,7 @@ void dp_enable_link_phy(
                                pipes[i].clock_source->funcs->program_pix_clk(
                                                        pipes[i].clock_source,
                                                        &pipes[i].stream_res.pix_clk_params,
+                                                       dp_get_link_encoding_format(link_settings),
                                                        &pipes[i].pll_settings);
                        }
                }

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index d55da1ab1ac2e772f56946e45e0d2a17ae082a1f..213de8cabfadb39e48a36037ab89e3cde03afdbc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -838,6 +838,7 @@ static void dce112_program_pixel_clk_resync(
 static bool dce110_program_pix_clk(
                struct clock_source *clock_source,
                struct pixel_clk_params *pix_clk_params,
+               enum dp_link_encoding encoding,
                struct pll_settings *pll_settings)
 {
        struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -911,6 +912,7 @@ static bool dce110_program_pix_clk(
 static bool dce112_program_pix_clk(
                struct clock_source *clock_source,
                struct pixel_clk_params *pix_clk_params,
+               enum dp_link_encoding encoding,
                struct pll_settings *pll_settings)
 {
        struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -970,6 +972,7 @@ static bool dce112_program_pix_clk(
 static bool dcn31_program_pix_clk(
                struct clock_source *clock_source,
                struct pixel_clk_params *pix_clk_params,
+               enum dp_link_encoding encoding,
                struct pll_settings *pll_settings)
 {
        struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -993,9 +996,14 @@ static bool dcn31_program_pix_clk(
 #if defined(CONFIG_DRM_AMD_DC_DCN)
                /* Enable DTO */
                if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
-                       REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
-                                       DP_DTO0_ENABLE, 1,
-                                       PIPE0_DTO_SRC_SEL, 1);
+                       if (encoding == DP_128b_132b_ENCODING)
+                               REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
+                                               DP_DTO0_ENABLE, 1,
+                                               PIPE0_DTO_SRC_SEL, 2);
+                       else
+                               REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
+                                               DP_DTO0_ENABLE, 1,
+                                               PIPE0_DTO_SRC_SEL, 1);
                else
                        REG_UPDATE(PIXEL_RATE_CNTL[inst],
                                        DP_DTO0_ENABLE, 1);
@@ -1198,12 +1206,13 @@ const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
 static bool dcn20_program_pix_clk(
                struct clock_source *clock_source,
                struct pixel_clk_params *pix_clk_params,
+               enum dp_link_encoding encoding,
                struct pll_settings *pll_settings)
 {
        struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
        unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
 
-       dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
+       dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
 
        if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
                        clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
@@ -1243,6 +1252,7 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = {
 static bool dcn3_program_pix_clk(
                struct clock_source *clock_source,
                struct pixel_clk_params *pix_clk_params,
+               enum dp_link_encoding encoding,
                struct pll_settings *pll_settings)
 {
        struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -1265,7 +1275,7 @@ static bool dcn3_program_pix_clk(
                REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
        } else
                // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
-               dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
+               dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
 
        return true;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index e69c942c8345b0c0561478f5ab2cad6e955d6b40..38a67051d470f24cd1407a0a828b035760b7d36c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1435,6 +1435,7 @@ static enum dc_status dce110_enable_stream_timing(
                if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
                                pipe_ctx->clock_source,
                                &pipe_ctx->stream_res.pix_clk_params,
+                               dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings),
                                &pipe_ctx->pll_settings)) {
                        BREAK_TO_DEBUGGER();
                        return DC_ERROR_UNEXPECTED;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7a3812604e4bfa3d03b43abe76a01c29d0d1fee4..bed783747f169b522e7ff561204b8bf4d32cd4e9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -892,6 +892,7 @@ enum dc_status dcn10_enable_stream_timing(
        if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
                        pipe_ctx->clock_source,
                        &pipe_ctx->stream_res.pix_clk_params,
+                       dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings),
                        &pipe_ctx->pll_settings)) {
                BREAK_TO_DEBUGGER();
                return DC_ERROR_UNEXPECTED;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 3b26962637d0c539b4e86a2729c95cb17007b3a0..3e44b799842959a8a4357a0f680b889d7b4292a5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -700,6 +700,7 @@ enum dc_status dcn20_enable_stream_timing(
        if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
                        pipe_ctx->clock_source,
                        &pipe_ctx->stream_res.pix_clk_params,
+                       dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings),
                        &pipe_ctx->pll_settings)) {
                BREAK_TO_DEBUGGER();
                return DC_ERROR_UNEXPECTED;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
index e2b3a2c7a927009c05bdd0e1a7dda1cf9781ae79..8f8ac8e29ed0897de24636172b7fa3f4746493c0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
@@ -160,8 +160,11 @@ struct calc_pll_clock_source {
 struct clock_source_funcs {
        bool (*cs_power_down)(
                        struct clock_source *);
-       bool (*program_pix_clk)(struct clock_source *,
-                       struct pixel_clk_params *, struct pll_settings *);
+       bool (*program_pix_clk)(
+                       struct clock_source *,
+                       struct pixel_clk_params *,
+                       enum dp_link_encoding encoding,
+                       struct pll_settings *);
        uint32_t (*get_pix_clk_dividers)(
                        struct clock_source *,
                        struct pixel_clk_params *,