ARM: rmobile: Remove Watchdog and CPG settings on Gen3
authorHiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Tue, 25 Sep 2018 09:48:03 +0000 (18:48 +0900)
committerMarek Vasut <marex@denx.de>
Thu, 18 Oct 2018 17:07:46 +0000 (19:07 +0200)
This code is unnecessary, because these registers are set by the
initial program loader (IPL).

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
board/renesas/draak/draak.c
board/renesas/salvator-x/salvator-x.c
board/renesas/ulcb/ulcb.c

index f9ae74a..71fd500 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CPGWPCR        0xE6150904
-#define CPGWPR  0xE6150900
-
-#define CLK2MHZ(clk)   (clk / 1000 / 1000)
 void s_init(void)
 {
-       struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
-       struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
-       /* Watchdog init */
-       writel(0xA5A5A500, &rwdt->rwtcsra);
-       writel(0xA5A5A500, &swdt->swtcsra);
-
-       writel(0x5A5AFFFF, CPGWPR);
-       writel(0xA5A50000, CPGWPCR);
 }
 
 #define GSX_MSTP112            BIT(12) /* 3DG */
index cb5228a..296aa90 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CPGWPCR        0xE6150904
-#define CPGWPR  0xE6150900
-
-#define CLK2MHZ(clk)   (clk / 1000 / 1000)
 void s_init(void)
 {
-       struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
-       struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
-       /* Watchdog init */
-       writel(0xA5A5A500, &rwdt->rwtcsra);
-       writel(0xA5A5A500, &swdt->swtcsra);
-
-       writel(0x5A5AFFFF, CPGWPR);
-       writel(0xA5A50000, CPGWPCR);
 }
 
 #define GSX_MSTP112            BIT(12) /* 3DG */
index fca6eae..a7ca274 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CPGWPCR        0xE6150904
-#define CPGWPR  0xE6150900
-
-#define CLK2MHZ(clk)   (clk / 1000 / 1000)
 void s_init(void)
 {
-       struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
-       struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
-       /* Watchdog init */
-       writel(0xA5A5A500, &rwdt->rwtcsra);
-       writel(0xA5A5A500, &swdt->swtcsra);
-
-       writel(0x5A5AFFFF, CPGWPR);
-       writel(0xA5A50000, CPGWPCR);
 }
 
 #define GSX_MSTP112            BIT(12) /* 3DG */