u32 mact_entry;
int res, err;
+ if (netif_is_bridge_master(v->obj.orig_dev)) {
+ sparx5_mact_learn(spx5, PGID_CPU, v->addr, v->vid);
+ return 0;
+ }
+
/* When VLAN unaware the vlan value is not parsed and we receive vid 0.
* Fall back to bridge vid 1.
*/
u32 mact_entry, res, pgid_entry[3];
int err;
+ if (netif_is_bridge_master(v->obj.orig_dev)) {
+ sparx5_mact_forget(spx5, v->addr, v->vid);
+ return 0;
+ }
+
if (!br_vlan_enabled(spx5->hw_bridge_dev))
vid = 1;
else
SWITCHDEV_OBJ_PORT_VLAN(obj));
break;
case SWITCHDEV_OBJ_ID_PORT_MDB:
+ case SWITCHDEV_OBJ_ID_HOST_MDB:
err = sparx5_handle_port_mdb_add(dev, nb,
SWITCHDEV_OBJ_PORT_MDB(obj));
break;
SWITCHDEV_OBJ_PORT_VLAN(obj)->vid);
break;
case SWITCHDEV_OBJ_ID_PORT_MDB:
+ case SWITCHDEV_OBJ_ID_HOST_MDB:
err = sparx5_handle_port_mdb_del(dev, nb,
SWITCHDEV_OBJ_PORT_MDB(obj));
break;