ARM: dts: imx6sx-udoo-neo: Use new pin names with DCE/DTE for UART pins

Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this
is to distinguish the DCE/DTE functions.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
index 25d4aa9..ee64565 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
@@ -235,28 +235,28 @@
 
        pinctrl_uart1: uart1grp {
                fsl,pins =
-                       <MX6SX_PAD_GPIO1_IO04__UART1_TX         0x1b0b1>,
-                       <MX6SX_PAD_GPIO1_IO05__UART1_RX         0x1b0b1>;
+                       <MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX     0x1b0b1>,
+                       <MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX     0x1b0b1>;
        };
 
        pinctrl_uart2: uart2grp {
                fsl,pins =
-                       <MX6SX_PAD_GPIO1_IO06__UART2_TX         0x1b0b1>,
-                       <MX6SX_PAD_GPIO1_IO07__UART2_RX         0x1b0b1>;
+                       <MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX     0x1b0b1>,
+                       <MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX     0x1b0b1>;
        };
 
        pinctrl_uart3: uart3grp {
                fsl,pins =
-                       <MX6SX_PAD_SD3_DATA4__UART3_RX          0x13059>,
-                       <MX6SX_PAD_SD3_DATA5__UART3_TX          0x13059>,
-                       <MX6SX_PAD_SD3_DATA6__UART3_RTS_B       0x13059>,
-                       <MX6SX_PAD_SD3_DATA7__UART3_CTS_B       0x13059>;
+                       <MX6SX_PAD_SD3_DATA4__UART3_DCE_RX      0x13059>,
+                       <MX6SX_PAD_SD3_DATA5__UART3_DCE_TX      0x13059>,
+                       <MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS     0x13059>,
+                       <MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS     0x13059>;
        };
 
        pinctrl_uart5: uart5grp {
                fsl,pins =
-                       <MX6SX_PAD_SD4_DATA4__UART5_RX          0x1b0b1>,
-                       <MX6SX_PAD_SD4_DATA5__UART5_TX          0x1b0b1>;
+                       <MX6SX_PAD_SD4_DATA4__UART5_DCE_RX      0x1b0b1>,
+                       <MX6SX_PAD_SD4_DATA5__UART5_DCE_TX      0x1b0b1>;
        };
 
        pinctrl_uart6: uart6grp {
@@ -265,10 +265,10 @@
                        <MX6SX_PAD_CSI_DATA01__UART6_DSR_B      0x1b0b1>,
                        <MX6SX_PAD_CSI_DATA02__UART6_DTR_B      0x1b0b1>,
                        <MX6SX_PAD_CSI_DATA03__UART6_DCD_B      0x1b0b1>,
-                       <MX6SX_PAD_CSI_DATA04__UART6_RX         0x1b0b1>,
-                       <MX6SX_PAD_CSI_DATA05__UART6_TX         0x1b0b1>,
-                       <MX6SX_PAD_CSI_DATA06__UART6_RTS_B      0x1b0b1>,
-                       <MX6SX_PAD_CSI_DATA07__UART6_CTS_B      0x1b0b1>;
+                       <MX6SX_PAD_CSI_DATA04__UART6_DCE_RX     0x1b0b1>,
+                       <MX6SX_PAD_CSI_DATA05__UART6_DCE_TX     0x1b0b1>,
+                       <MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS    0x1b0b1>,
+                       <MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS    0x1b0b1>;
        };
 
        pinctrl_otg1_reg: otg1grp {