radeonsi/gfx11: limit CP DMA to max 32KB sizes

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>

diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c
index 2b80eeb..9387dc4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -396,6 +396,7 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
          compute_min_size = 4 * 1024;
       }
 
+      /* TODO: use compute for unaligned big sizes */
       if (method == SI_AUTO_SELECT_CLEAR_METHOD && (
            clear_value_size > 4 ||
            (clear_value_size == 4 && offset % 4 == 0 && size > compute_min_size))) {
@@ -464,6 +465,7 @@ void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct p
    si_improve_sync_flags(sctx, dst, src, &flags);
 
    /* Only use compute for VRAM copies on dGPUs. */
+   /* TODO: use compute for unaligned big sizes */
    if (sctx->screen->info.has_dedicated_vram && si_resource(dst)->domains & RADEON_DOMAIN_VRAM &&
        si_resource(src)->domains & RADEON_DOMAIN_VRAM && size > compute_min_size &&
        dst_offset % 4 == 0 && src_offset % 4 == 0 && size % 4 == 0) {

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index d6f3669..c614965 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -43,6 +43,7 @@
 static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
 {
    unsigned max =
+      sctx->chip_class >= GFX11 ? 32767 :
       sctx->chip_class >= GFX9 ? S_415_BYTE_COUNT_GFX9(~0u) : S_415_BYTE_COUNT_GFX6(~0u);
 
    /* make it aligned for optimal performance */
@@ -402,6 +403,9 @@ void si_cp_dma_prefetch(struct si_context *sctx, struct pipe_resource *buf,
 
    assert(sctx->chip_class >= GFX7);
 
+   if (sctx->chip_class >= GFX11)
+      size = MIN2(size, 32768 - SI_CPDMA_ALIGNMENT);
+
    /* The prefetch address and size must be aligned, so that we don't have to apply
     * the complicated hw bug workaround.
     *