enable wave32 for compute shaders (GFX10+)
``dccmsaa``
enable DCC for MSAA images
- ``dccstores``
- enable DCC for storage images (for performance testing on GFX10.3 only)
``dfsm``
enable DFSM
``gewave32``
RADV_PERFTEST_DFSM = 1u << 6,
RADV_PERFTEST_NO_SAM = 1u << 7,
RADV_PERFTEST_SAM = 1u << 8,
- RADV_PERFTEST_DCC_STORES = 1u << 9,
};
bool radv_init_trace(struct radv_device *device);
{"cswave32", RADV_PERFTEST_CS_WAVE_32}, {"pswave32", RADV_PERFTEST_PS_WAVE_32},
{"gewave32", RADV_PERFTEST_GE_WAVE_32}, {"dfsm", RADV_PERFTEST_DFSM},
{"nosam", RADV_PERFTEST_NO_SAM}, {"sam", RADV_PERFTEST_SAM},
- {"dccstores", RADV_PERFTEST_DCC_STORES}, {NULL, 0}};
+ {NULL, 0}};
const char *
radv_get_perftest_option_name(int id)
bool
radv_image_use_dcc_image_stores(const struct radv_device *device, const struct radv_image *image)
{
- /*
- * TODO: Enable on more HW. DIMGREY and VANGOGH need a workaround and
- * we need more perf analysis.
- * https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6796#note_643853
- */
- return device->physical_device->rad_info.chip_class == GFX10 ||
- (device->physical_device->rad_info.chip_class == GFX10_3 &&
- (device->instance->perftest_flags & RADV_PERFTEST_DCC_STORES));
+ return device->physical_device->rad_info.chip_class >= GFX10;
}
/*