clk: qcom: msm8996-cpu: Rename DIV_2_INDEX to SMUX_INDEX

The parent at this index is the secondary mux, which can connect
not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX
to better reflect the parent.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-2-y.oudjana@protonmail.com

diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index 4a4fde8dd12dd9443bf4f7ffd286cd45408dd9f0..5dc68dc3621f879dcdeaa1741b3f776b73c233e3 100644 (file)
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -61,7 +61,7 @@
 #include "clk-regmap.h"
 
 enum _pmux_input {
-       DIV_2_INDEX = 0,
+       SMUX_INDEX = 0,
        PLL_INDEX,
        ACD_INDEX,
        ALT_INDEX,
@@ -468,7 +468,7 @@ static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
        case POST_RATE_CHANGE:
                if (cnd->new_rate < DIV_2_THRESHOLD)
                        ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
-                                                         DIV_2_INDEX);
+                                                         SMUX_INDEX);
                else
                        ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
                                                          ACD_INDEX);