#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
#define NOUVEAU_GETPARAM_PTIMER_TIME 14
+#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
struct drm_nouveau_getparam {
uint64_t param;
uint64_t value;
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
+#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
+#define NOUVEAU_GEM_TILE_16BPP 0x00000001
+#define NOUVEAU_GEM_TILE_32BPP 0x00000002
+#define NOUVEAU_GEM_TILE_ZETA 0x00000004
+#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
+
struct drm_nouveau_gem_info {
uint32_t handle;
uint32_t domain;
nvbo->offset = arg->offset;
nvbo->map_handle = arg->map_handle;
nvbo->base.tile_mode = arg->tile_mode;
- nvbo->base.tile_flags = arg->tile_flags;
+ /* XXX - flag inverted for backwards compatibility */
+ nvbo->base.tile_flags = arg->tile_flags ^ NOUVEAU_GEM_TILE_NONCONTIG;
return 0;
}
info->tile_mode = nvbo->base.tile_mode;
info->tile_flags = nvbo->base.tile_flags;
+ /* XXX - flag inverted for backwards compatibility */
+ info->tile_flags ^= NOUVEAU_GEM_TILE_NONCONTIG;
+ if (!nvdev->has_bo_usage)
+ info->tile_flags &= NOUVEAU_GEM_TILE_LAYOUT_MASK;
ret = drmCommandWriteRead(nvdev->fd, DRM_NOUVEAU_GEM_NEW,
&req, sizeof(req));
#define NOUVEAU_BO_IFLUSH (1 << 15)
#define NOUVEAU_BO_DUMMY (1 << 31)
+#define NOUVEAU_BO_TILE_LAYOUT_MASK 0x0000ff00
+#define NOUVEAU_BO_TILE_16BPP 0x00000001
+#define NOUVEAU_BO_TILE_32BPP 0x00000002
+#define NOUVEAU_BO_TILE_ZETA 0x00000004
+#define NOUVEAU_BO_TILE_SCANOUT 0x00000008
+
struct nouveau_bo {
struct nouveau_device *device;
uint32_t handle;
}
nvdev->base.chipset = value;
+ ret = nouveau_device_get_param(&nvdev->base,
+ NOUVEAU_GETPARAM_HAS_BO_USAGE, &value);
+ if (!ret)
+ nvdev->has_bo_usage = value;
+
*dev = &nvdev->base;
return 0;
}
drm_context_t ctx;
drmLock *lock;
int needs_close;
+ int has_bo_usage;
};
#define nouveau_device(n) ((struct nouveau_device_priv *)(n))