mailbox: ti-msgmgr: Fill non-message tx data fields with 0x0

Sec proxy/message manager data buffer is 60 bytes with the last of the
registers indicating transmission completion. This however poses a bit
of a challenge.

The backing memory for sec_proxy / message manager is regular memory,
and all sec proxy does is to trigger a burst of all 60 bytes of data
over to the target thread backing ring accelerator. It doesn't do a
memory scrub when it moves data out in the burst. When we transmit
multiple messages, remnants of previous message is also transmitted
which results in some random data being set in TISCI fields of
messages that have been expanded forward.

The entire concept of backward compatibility hinges on the fact that
the unused message fields remain 0x0 allowing for 0x0 value to be
specially considered when backward compatibility of message extension
is done.

So, instead of just writing the completion register, we continue
to fill the message buffer up with 0x0 (note: for partial message
involving completion, we already do this).

This allows us to scale and introduce ABI changes back also work with
other boot stages that may have left data in the internal memory.

While at this, be consistent and explicit with the data_reg pointer
increment.

Fixes: aace66b170ce ("mailbox: Introduce TI message manager driver")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c
index ddac423..03048cb 100644 (file)
--- a/drivers/mailbox/ti-msgmgr.c
+++ b/drivers/mailbox/ti-msgmgr.c
@@ -430,14 +430,20 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data)
                /* Ensure all unused data is 0 */
                data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes));
                writel(data_trail, data_reg);
-               data_reg++;
+               data_reg += sizeof(u32);
        }
+
        /*
         * 'data_reg' indicates next register to write. If we did not already
         * write on tx complete reg(last reg), we must do so for transmit
+        * In addition, we also need to make sure all intermediate data
+        * registers(if any required), are reset to 0 for TISCI backward
+        * compatibility to be maintained.
         */
-       if (data_reg <= qinst->queue_buff_end)
-               writel(0, qinst->queue_buff_end);
+       while (data_reg <= qinst->queue_buff_end) {
+               writel(0, data_reg);
+               data_reg += sizeof(u32);
+       }
 
        /* If we are in polled mode, wait for a response before proceeding */
        if (ti_msgmgr_chan_has_polled_queue_rx(message->chan_rx))