clk: qcom: gcc: Add support for a new frequency for SC7180

There is a requirement to support 51.2MHz from GPLL6 for qup clocks,
thus update the frequency table and parent data/map to use the GPLL6
source PLL.

Fixes: 17269568f7267 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1589709861-27580-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index 6a51b5b..7338052 100644 (file)
--- a/drivers/clk/qcom/gcc-sc7180.c
+++ b/drivers/clk/qcom/gcc-sc7180.c
@@ -390,6 +390,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
        F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
        F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
        F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
+       F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
        F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
        F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
        F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
@@ -405,8 +406,8 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 
 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
        .name = "gcc_qupv3_wrap0_s0_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -414,15 +415,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
        .cmd_rcgr = 0x17034,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
        .name = "gcc_qupv3_wrap0_s1_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -430,15 +431,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
        .cmd_rcgr = 0x17164,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
        .name = "gcc_qupv3_wrap0_s2_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -446,15 +447,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
        .cmd_rcgr = 0x17294,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
        .name = "gcc_qupv3_wrap0_s3_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -462,15 +463,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
        .cmd_rcgr = 0x173c4,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
        .name = "gcc_qupv3_wrap0_s4_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -478,15 +479,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
        .cmd_rcgr = 0x174f4,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
        .name = "gcc_qupv3_wrap0_s5_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -494,15 +495,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
        .cmd_rcgr = 0x17624,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
        .name = "gcc_qupv3_wrap1_s0_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -510,15 +511,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
        .cmd_rcgr = 0x18018,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
        .name = "gcc_qupv3_wrap1_s1_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -526,15 +527,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
        .cmd_rcgr = 0x18148,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
        .name = "gcc_qupv3_wrap1_s2_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -542,15 +543,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
        .cmd_rcgr = 0x18278,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
        .name = "gcc_qupv3_wrap1_s3_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -558,15 +559,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
        .cmd_rcgr = 0x183a8,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
        .name = "gcc_qupv3_wrap1_s4_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -574,15 +575,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
        .cmd_rcgr = 0x184d8,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 };
 
 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
        .name = "gcc_qupv3_wrap1_s5_clk_src",
-       .parent_data = gcc_parent_data_0,
-       .num_parents = 4,
+       .parent_data = gcc_parent_data_1,
+       .num_parents = ARRAY_SIZE(gcc_parent_data_1),
        .ops = &clk_rcg2_ops,
 };
 
@@ -590,7 +591,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
        .cmd_rcgr = 0x18608,
        .mnd_width = 16,
        .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
+       .parent_map = gcc_parent_map_1,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
        .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 };