Migrate the AArch64 TargetRegisterInfo to its TargetMachine

implementation. This requires a bit of scaffolding and a few fixups
that'll go away once all of the ports have been migrated.

llvm-svn: 232103

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 8e0af2d..581a3b9 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -31,7 +31,7 @@ using namespace llvm;
 
 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
     : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
-      RI(STI.getTargetTriple()), Subtarget(STI) {}
+      Subtarget(STI) {}
 
 /// GetInstSize - Return the number of bytes of code the specified
 /// instruction may be.  This returns the maximum number of bytes.
@@ -375,7 +375,8 @@ bool AArch64InstrInfo::canInsertSelect(
   // Check register classes.
   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *RC =
-      RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
+      Subtarget.getRegisterInfo()->getCommonSubClass(MRI.getRegClass(TrueReg),
+                                                     MRI.getRegClass(FalseReg));
   if (!RC)
     return false;
 
@@ -612,7 +613,7 @@ bool
 AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
                                                   MachineInstr *MIb,
                                                   AliasAnalysis *AA) const {
-  const TargetRegisterInfo *TRI = &getRegisterInfo();
+  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   unsigned BaseRegA = 0, BaseRegB = 0;
   int OffsetA = 0, OffsetB = 0;
   int WidthA = 0, WidthB = 0;
@@ -865,7 +866,7 @@ bool AArch64InstrInfo::optimizeCompareInstr(
     return false;
 
   bool CheckOnlyCCWrites = false;
-  const TargetRegisterInfo *TRI = &getRegisterInfo();
+  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   if (modifiesConditionCode(MI, CmpInstr, CheckOnlyCCWrites, TRI))
     return false;
 
@@ -1513,7 +1514,7 @@ void AArch64InstrInfo::copyPhysRegTuple(
     llvm::ArrayRef<unsigned> Indices) const {
   assert(Subtarget.hasNEON() &&
          "Unexpected register copy without NEON");
-  const TargetRegisterInfo *TRI = &getRegisterInfo();
+  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
   uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned NumRegs = Indices.size();
@@ -1537,10 +1538,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator I, DebugLoc DL,
                                    unsigned DestReg, unsigned SrcReg,
                                    bool KillSrc) const {
+  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   if (AArch64::GPR32spRegClass.contains(DestReg) &&
       (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
-    const TargetRegisterInfo *TRI = &getRegisterInfo();
-
     if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
       // If either operand is WSP, expand to ADD #0.
       if (Subtarget.hasZeroCycleRegMove()) {
@@ -1694,10 +1694,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (AArch64::FPR64RegClass.contains(DestReg) &&
       AArch64::FPR64RegClass.contains(SrcReg)) {
     if(Subtarget.hasNEON()) {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
-                                       &AArch64::FPR128RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
-                                      &AArch64::FPR128RegClass);
+      DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::dsub,
+                                         &AArch64::FPR128RegClass);
+      SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::dsub,
+                                        &AArch64::FPR128RegClass);
       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
           .addReg(SrcReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
@@ -1711,10 +1711,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (AArch64::FPR32RegClass.contains(DestReg) &&
       AArch64::FPR32RegClass.contains(SrcReg)) {
     if(Subtarget.hasNEON()) {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
-                                       &AArch64::FPR128RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
-                                      &AArch64::FPR128RegClass);
+      DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
+                                         &AArch64::FPR128RegClass);
+      SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
+                                        &AArch64::FPR128RegClass);
       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
           .addReg(SrcReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
@@ -1728,18 +1728,18 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (AArch64::FPR16RegClass.contains(DestReg) &&
       AArch64::FPR16RegClass.contains(SrcReg)) {
     if(Subtarget.hasNEON()) {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
-                                       &AArch64::FPR128RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
-                                      &AArch64::FPR128RegClass);
+      DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
+                                         &AArch64::FPR128RegClass);
+      SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
+                                        &AArch64::FPR128RegClass);
       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
           .addReg(SrcReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     } else {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
-                                       &AArch64::FPR32RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
-                                      &AArch64::FPR32RegClass);
+      DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
+                                         &AArch64::FPR32RegClass);
+      SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
+                                        &AArch64::FPR32RegClass);
       BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     }
@@ -1749,18 +1749,18 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (AArch64::FPR8RegClass.contains(DestReg) &&
       AArch64::FPR8RegClass.contains(SrcReg)) {
     if(Subtarget.hasNEON()) {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
+      DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
                                        &AArch64::FPR128RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
-                                      &AArch64::FPR128RegClass);
+      SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
+                                        &AArch64::FPR128RegClass);
       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
           .addReg(SrcReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     } else {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
-                                       &AArch64::FPR32RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
-                                      &AArch64::FPR32RegClass);
+      DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
+                                         &AArch64::FPR32RegClass);
+      SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
+                                        &AArch64::FPR32RegClass);
       BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     }
@@ -2946,7 +2946,8 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr *MI) const {
   // Convert only when the condition code is not modified between
   // the CSINC and the branch. The CC may be used by other
   // instructions in between.
-  if (modifiesConditionCode(DefMI, MI, CheckOnlyCCWrites, &getRegisterInfo()))
+  if (modifiesConditionCode(DefMI, MI, CheckOnlyCCWrites,
+                            Subtarget.getRegisterInfo()))
     return false;
   MachineBasicBlock &RefToMBB = *MBB;
   MachineBasicBlock *TBB = MI->getOperand(TargetBBInMI).getMBB();

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index fa4b8b7..0afc4f0 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -34,17 +34,11 @@ class AArch64InstrInfo : public AArch64GenInstrInfo {
     MOSuppressPair = 1
   };
 
-  const AArch64RegisterInfo RI;
   const AArch64Subtarget &Subtarget;
 
 public:
   explicit AArch64InstrInfo(const AArch64Subtarget &STI);
 
-  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
-  /// such, whenever a client has an instance of instruction info, it should
-  /// always be able to get register info as well (through this method).
-  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
-
   unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
 
   bool isAsCheapAsAMove(const MachineInstr *MI) const override;

diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 6f5de36..9dfaf6b 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -38,8 +38,8 @@ static cl::opt<bool>
 ReserveX18("aarch64-reserve-x18", cl::Hidden,
           cl::desc("Reserve X18, making it unavailable as GPR"));
 
-AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
-    : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
+AArch64RegisterInfo::AArch64RegisterInfo(StringRef TargetTriple)
+    : AArch64GenRegisterInfo(AArch64::LR), TT(TargetTriple) {}
 
 const MCPhysReg *
 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {

diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
index cb752b3..ca99a25 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -26,10 +26,10 @@ class Triple;
 
 struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
 private:
-  const Triple &TT;
+  const Triple TT;
 
 public:
-  AArch64RegisterInfo(const Triple &TT);
+  AArch64RegisterInfo(StringRef TargetTriple);
 
   bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
 

diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index c613025..7b04b1a 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -14,6 +14,7 @@
 #include "AArch64InstrInfo.h"
 #include "AArch64PBQPRegAlloc.h"
 #include "AArch64Subtarget.h"
+#include "AArch64TargetMachine.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/IR/GlobalValue.h"
@@ -45,12 +46,13 @@ AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
 AArch64Subtarget::AArch64Subtarget(const std::string &TT,
                                    const std::string &CPU,
                                    const std::string &FS,
-                                   const TargetMachine &TM, bool LittleEndian)
+                                   const AArch64TargetMachine &TM,
+                                   bool LittleEndian)
     : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
       HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false),
       HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
-      IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
-      InstrInfo(initializeSubtargetDependencies(FS)),
+      IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), TM(TM),
+      FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS)),
       TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}
 
 /// ClassifyGlobalReference - Find the target operand flags that describe
@@ -129,3 +131,7 @@ AArch64Subtarget::getCustomPBQPConstraints() const {
 
   return llvm::make_unique<A57ChainingConstraint>();
 }
+
+const AArch64RegisterInfo *AArch64Subtarget::getRegisterInfo() const {
+  return getTargetMachine().getRegisterInfo();
+}

diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index e47d13a..14cc5d2 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -56,6 +56,7 @@ protected:
   /// TargetTriple - What processor and OS we're targeting.
   Triple TargetTriple;
 
+  const AArch64TargetMachine &TM;
   AArch64FrameLowering FrameLowering;
   AArch64InstrInfo InstrInfo;
   AArch64SelectionDAGInfo TSInfo;
@@ -70,7 +71,7 @@ public:
   /// This constructor initializes the data members to match that
   /// of the specified triple.
   AArch64Subtarget(const std::string &TT, const std::string &CPU,
-                   const std::string &FS, const TargetMachine &TM,
+                   const std::string &FS, const AArch64TargetMachine &TM,
                    bool LittleEndian);
 
   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
@@ -83,9 +84,8 @@ public:
     return &TLInfo;
   }
   const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
-  const AArch64RegisterInfo *getRegisterInfo() const override {
-    return &getInstrInfo()->getRegisterInfo();
-  }
+  const AArch64TargetMachine &getTargetMachine() const { return TM; }
+  const AArch64RegisterInfo *getRegisterInfo() const override;
   const Triple &getTargetTriple() const { return TargetTriple; }
   bool enableMachineScheduler() const override { return true; }
   bool enablePostMachineScheduler() const override {

diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index ed948cb..5bb2f9e 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -127,6 +127,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
     : LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
                         Options, RM, CM, OL),
       TLOF(createTLOF(Triple(getTargetTriple()))),
+      RI(TT),
       Subtarget(TT, CPU, FS, *this, LittleEndian),
       isLittle(LittleEndian) {
   initAsmInfo();

diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index e73aa87..89472e4 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -24,6 +24,7 @@ namespace llvm {
 class AArch64TargetMachine : public LLVMTargetMachine {
 protected:
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
+  AArch64RegisterInfo RI;
   AArch64Subtarget Subtarget;
   mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
 
@@ -39,6 +40,7 @@ public:
     return &Subtarget;
   }
   const AArch64Subtarget *getSubtargetImpl(const Function &F) const override;
+  const AArch64RegisterInfo *getRegisterInfo() const { return &RI; }
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;