soc: renesas: r8a77980-sysc: Correct names of A2DP[01] power domains
authorGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 29 Nov 2018 10:56:17 +0000 (11:56 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 13 Dec 2019 07:52:17 +0000 (08:52 +0100)
[ Upstream commit 97473bc85b22ac610b1810b6a9a4669a6cb0b7b0 ]

The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018)
renamed the A2PD0 and A2DP0 power domains on R-Car V3H to A2DP0 resp.
A2DP1.

As these definitions are not yet used from DT, they can just be renamed.

Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain definitions")
Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/soc/renesas/r8a77980-sysc.c
include/dt-bindings/power/r8a77980-sysc.h

index 9265fb5..dbb2621 100644 (file)
@@ -38,8 +38,8 @@ static const struct rcar_sysc_area r8a77980_areas[] __initconst = {
        { "a2sc2",      0x400, 8, R8A77980_PD_A2SC2,    R8A77980_PD_A3IR },
        { "a2sc3",      0x400, 9, R8A77980_PD_A2SC3,    R8A77980_PD_A3IR },
        { "a2sc4",      0x400, 10, R8A77980_PD_A2SC4,   R8A77980_PD_A3IR },
-       { "a2pd0",      0x400, 11, R8A77980_PD_A2PD0,   R8A77980_PD_A3IR },
-       { "a2pd1",      0x400, 12, R8A77980_PD_A2PD1,   R8A77980_PD_A3IR },
+       { "a2dp0",      0x400, 11, R8A77980_PD_A2DP0,   R8A77980_PD_A3IR },
+       { "a2dp1",      0x400, 12, R8A77980_PD_A2DP1,   R8A77980_PD_A3IR },
        { "a2cn",       0x400, 13, R8A77980_PD_A2CN,    R8A77980_PD_A3IR },
        { "a3vip",      0x2c0, 0, R8A77980_PD_A3VIP,    R8A77980_PD_ALWAYS_ON },
        { "a3vip1",     0x300, 0, R8A77980_PD_A3VIP1,   R8A77980_PD_A3VIP },
index 2c90c12..7bebe7e 100644 (file)
@@ -15,8 +15,8 @@
 #define R8A77980_PD_A2SC2              0
 #define R8A77980_PD_A2SC3              1
 #define R8A77980_PD_A2SC4              2
-#define R8A77980_PD_A2PD0              3
-#define R8A77980_PD_A2PD1              4
+#define R8A77980_PD_A2DP0              3
+#define R8A77980_PD_A2DP1              4
 #define R8A77980_PD_CA53_CPU0          5
 #define R8A77980_PD_CA53_CPU1          6
 #define R8A77980_PD_CA53_CPU2          7