powerpc/mpc8xxx: Enable calculation for fixed DDR chips

We used to have fixed parameters for soldered DDR chips. This patch
introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing
data from DDR chip datasheet, implemneted in board-specific files or header
files.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/README b/README
index 2da0f96..1e2d4d3 100644 (file)
--- a/README
+++ b/README
@@ -2948,6 +2948,12 @@ Low Level (hardware related) configuration options:
                one, specify here. Note that the value must resolve
                to something your driver can deal with.
 
+- CONFIG_SYS_DDR_RAW_TIMING
+               Get DDR timing information from other than SPD. Common with
+               soldered DDR chips onboard without SPD. DDR raw timing
+               parameters are extracted from datasheet and hard-coded into
+               header files or board specific files.
+
 - CONFIG_SYS_83XX_DDR_USES_CS0
                Only for 83xx systems. If specified, then DDR should
                be configured using CS0 and CS1 instead of CS2 and CS3.

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index f863f4a..53f0887 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -336,7 +336,9 @@ phys_size_t initdram(int board_type)
        }
 #endif
 
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if    defined(CONFIG_SPD_EEPROM)      || \
+       defined(CONFIG_DDR_SPD)         || \
+       defined(CONFIG_SYS_DDR_RAW_TIMING)
        dram_size = fsl_ddr_sdram();
 #else
        dram_size = fixed_sdram();

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
index 4a5a785..d1b4c4b 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
@@ -12,15 +12,24 @@ LIB = $(obj)libddr.o
 
 COBJS-$(CONFIG_FSL_DDR1)       += main.o util.o ctrl_regs.o options.o \
                                   lc_common_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR1)       += ddr1_dimm_params.o
 
 COBJS-$(CONFIG_FSL_DDR2)       += main.o util.o ctrl_regs.o options.o \
                                   lc_common_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR2)       += ddr2_dimm_params.o
 
 COBJS-$(CONFIG_FSL_DDR3)       += main.o util.o ctrl_regs.o options.o \
                                   lc_common_dimm_params.o
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+ifdef SPD
+COBJS-$(CONFIG_FSL_DDR1)       += ddr1_dimm_params.o
+COBJS-$(CONFIG_FSL_DDR2)       += ddr2_dimm_params.o
 COBJS-$(CONFIG_FSL_DDR3)       += ddr3_dimm_params.o
+endif
+
 
 SRCS   := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 1e866fe..f59aa33 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -14,6 +14,7 @@
 
 #include "common_timing_params.h"
 
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 /*
  * Bind the main DDR setup driver's generic names
  * to this specific DDR technology.
@@ -25,6 +26,7 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd,
 {
        return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
 }
+#endif
 
 /*
  * Data Structures
@@ -80,4 +82,9 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
 extern unsigned int mclk_to_picos(unsigned int mclk);
 extern unsigned int get_memory_clk_period_ps(void);
 extern unsigned int picos_to_mclk(unsigned int picos);
+
+/* board specific function */
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+                       unsigned int controller_number,
+                       unsigned int dimm_number);
 #endif

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 62a73dd..3c49fa9 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -325,6 +325,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 
        switch (start_step) {
        case STEP_GET_SPD:
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
                /* STEP 1:  Gather all DIMM SPD data */
                for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
                        fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
@@ -356,6 +357,17 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
                        }
                }
 
+#else
+       case STEP_COMPUTE_DIMM_PARMS:
+               for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+                       for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+                               dimm_params_t *pdimm =
+                                       &(pinfo->dimm_params[i][j]);
+                               fsl_ddr_get_dimm_params(pdimm, i, j);
+                       }
+               }
+               debug("Filling dimm parameters from board specific file\n");
+#endif
        case STEP_COMPUTE_COMMON_PARMS:
                /*
                 * STEP 3: Compute a common set of timing parameters