arm64: dts: imx93-11x11-evk: enable eqos

Enable EQoS function for imx93-11x11-evk board.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
index 69786c3..f37b6ef 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
@@ -35,6 +35,26 @@
        status = "okay";
 };
 
+&eqos {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eqos>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy1>;
+       status = "okay";
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-frequency = <5000000>;
+
+               ethphy1: ethernet-phy@1 {
+                       reg = <1>;
+                       eee-broken-1000t;
+               };
+       };
+};
+
 &lpuart1 { /* console */
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
@@ -65,6 +85,25 @@
 };
 
 &iomuxc {
+       pinctrl_eqos: eqosgrp {
+               fsl,pins = <
+                       MX93_PAD_ENET1_MDC__ENET_QOS_MDC                        0x57e
+                       MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO                      0x57e
+                       MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                  0x57e
+                       MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                  0x57e
+                       MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2                  0x57e
+                       MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3                  0x57e
+                       MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK  0x5fe
+                       MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL            0x57e
+                       MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0                  0x57e
+                       MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1                  0x57e
+                       MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                  0x57e
+                       MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3                  0x57e
+                       MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK  0x5fe
+                       MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL            0x57e
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX93_PAD_UART1_RXD__LPUART1_RX                  0x31e