Used by AMD GPU NGG line culling. We could use nir load
line width and viewport scale to calculate this in shader,
but this way needs expensive divide ops.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
case nir_intrinsic_load_lshs_vertex_stride_amd:
case nir_intrinsic_load_tcs_num_patches_amd:
case nir_intrinsic_load_hs_out_patch_data_offset_amd:
+ case nir_intrinsic_load_clip_half_line_width_amd:
result = ctx->abi->intrinsic_load(ctx->abi, instr->intrinsic);
break;
case nir_intrinsic_load_vertex_id_zero_base: {
case nir_intrinsic_load_ray_num_dss_rt_stacks_intel:
case nir_intrinsic_load_lshs_vertex_stride_amd:
case nir_intrinsic_load_hs_out_patch_data_offset_amd:
+ case nir_intrinsic_load_clip_half_line_width_amd:
is_divergent = false;
break;
# Per patch data offset in HS VRAM output buffer
system_value("hs_out_patch_data_offset_amd", 1)
+# line_width * 0.5 / abs(viewport_scale[2])
+system_value("clip_half_line_width_amd", 2)
+
# V3D-specific instrinc for tile buffer color reads.
#
# The hardware requires that we read the samples and components of a pixel