spi: cadence-quadspi: allow operations with cmd/addr buswidth >1

With the removal of the incorrect logic of cqspi_set_protocol(), ops with
cmd/addr buswidth >1 are now working correctly.

Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash using 1-4-4
operations.

DTR operations are currently untested, so we leave them disabled for now
(except for the previously allowed 8-8-8 ops).

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/20220420155616.281730-2-matthias.schiffer@ew.tq-group.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 8c12c6d..0f7e28e 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1347,13 +1347,7 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem,
                        return false;
                if (op->data.nbytes && op->data.buswidth != 8)
                        return false;
-       } else if (all_false) {
-               /* Only 1-1-X ops are supported without DTR */
-               if (op->cmd.nbytes && op->cmd.buswidth > 1)
-                       return false;
-               if (op->addr.nbytes && op->addr.buswidth > 1)
-                       return false;
-       } else {
+       } else if (!all_false) {
                /* Mixed DTR modes are not supported. */
                return false;
        }