radeonsi: Set SPI_SHADER_COL_FORMAT to what the pixel shader actually exports.

Instead of deriving it from the colour buffer formats only.

Fixes a number of piglit tests which export depth from the pixel shader.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index 29e8960..686ed05 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -134,7 +134,6 @@ struct r600_context {
        /* shader information */
        unsigned                        sprite_coord_enable;
        unsigned                        export_16bpc;
-       unsigned                        spi_shader_col_format;
        struct r600_textures_info       vs_samplers;
        struct r600_textures_info       ps_samplers;
        struct si_resource              *border_color_table;

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 4843330..52ecef9 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -478,6 +478,13 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
                if (cbuf >= 0 && cbuf < 8) {
                        struct r600_context *rctx = si_shader_ctx->rctx;
                        compressed = (si_shader_ctx->key.export_16bpc >> cbuf) & 0x1;
+
+                       if (compressed)
+                               si_shader_ctx->shader->spi_shader_col_format |=
+                                       V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
+                       else
+                               si_shader_ctx->shader->spi_shader_col_format |=
+                                       V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
                }
        }
 
@@ -759,6 +766,9 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
                last_args[6]= uint->zero;
                last_args[7]= uint->zero;
                last_args[8]= uint->zero;
+
+               si_shader_ctx->shader->spi_shader_col_format |=
+                       V_028714_SPI_SHADER_32_ABGR;
        }
 
        /* Specify whether the EXEC mask represents the valid mask */

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index 6f12e76..07b2f9f 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -94,6 +94,7 @@ struct si_pipe_shader {
        unsigned                        num_sgprs;
        unsigned                        num_vgprs;
        unsigned                        spi_ps_input_ena;
+       unsigned                        spi_shader_col_format;
        unsigned                        sprite_coord_enable;
        unsigned                        so_strides[4];
        struct si_shader_key            key;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index fd046c6..2ec8287 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1685,9 +1685,7 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
             max_comp_size <= 10) ||
            (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
                rctx->export_16bpc |= 1 << cb;
-               rctx->spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * cb);
-       } else
-               rctx->spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * cb);
+       }
 }
 
 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
@@ -1785,7 +1783,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
        /* build states */
        rctx->have_depth_fb = 0;
        rctx->export_16bpc = 0;
-       rctx->spi_shader_col_format = 0;
        for (int i = 0; i < state->nr_cbufs; i++) {
                si_cb(rctx, pm4, state, i);
        }
@@ -1815,8 +1812,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
        si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
        si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
        si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
-       si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
-                      rctx->spi_shader_col_format);
        si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
 
        si_pm4_set_state(rctx, framebuffer, pm4);

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 257bf1e..6178d26 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -202,6 +202,8 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
        else
                spi_shader_z_format = 0;
        si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
+       si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
+                      shader->spi_shader_col_format);
 
        va = r600_resource_va(ctx->screen, (void *)shader->bo);
        si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);