// is even/odd.
multiclass ACC_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
string asmstr> {
- let Predicates = [MMA] in {
+ let Predicates = [MMA, IsNotISAFuture] in {
def NAME :
XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs acc:$AT), IOL,
!strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
!strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+ let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
+ def NAME#W :
+ XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs wacc:$AT), IOL,
+ !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def WPP :
+ XX3Form_AT3_XAB6<opcode, xo, (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
+ !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
}
// Defines 4 instructions, masked/unmasked with masks 8, 4, 4 bits.
multiclass ACC_UM_M844_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
string asmstr> {
defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
- let Predicates = [MMA, PrefixInstrs] in {
+ let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PM#NAME :
MMIRR_XX3Form_XY4P8_XAB6<
opcode, !or(xo, 0x01), (outs acc:$AT),
IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
+ def PM#NAME#W :
+ MMIRR_XX3Form_XY4P8_XAB6<
+ opcode, !or(xo, 0x01), (outs wacc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#WPP :
+ MMIRR_XX3Form_XY4P8_XAB6<
+ opcode, xo, (outs wacc:$AT),
+ !con((ins wacc:$ATi),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
}
// Defines 4 instructions, masked/unmasked with masks 4, 4, 4 bits.
multiclass ACC_UM_M444_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
string asmstr> {
defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
- let Predicates = [MMA, PrefixInstrs] in {
+ let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PM#NAME :
MMIRR_XX3Form_XYP4_XAB6<
opcode, !or(xo, 0x01), (outs acc:$AT),
IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
+ def PM#NAME#W :
+ MMIRR_XX3Form_XYP4_XAB6<
+ opcode, !or(xo, 0x01), (outs wacc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#WPP :
+ MMIRR_XX3Form_XYP4_XAB6<
+ opcode, xo, (outs wacc:$AT),
+ !con((ins wacc:$ATi),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
}
// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.
multiclass ACC_UM_M244_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
string asmstr> {
defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
- let Predicates = [MMA, PrefixInstrs] in {
+ let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PM#NAME :
MMIRR_XX3Form_XY4P2_XAB6<
opcode, !or(xo, 0x01), (outs acc:$AT),
IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
+ def PM#NAME#W :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0x01), (outs wacc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#WPP :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, xo, (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
}
// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.
// Upper nibble of XO field for acc/non-acc version is 0x4/0x6.
multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
string asmstr> {
- let Predicates = [MMA] in {
+ let Predicates = [MMA, IsNotISAFuture] in {
def NAME :
XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), IOL,
!strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
!strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
- let Predicates = [MMA, PrefixInstrs] in {
+ let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PM#NAME :
MMIRR_XX3Form_XY4P2_XAB6<
opcode, xo, (outs acc:$AT),
IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+ let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
+ def NAME#W :
+ XX3Form_AT3_XAB6<opcode, xo, (outs wacc:$AT), IOL,
+ !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def WPP :
+ XX3Form_AT3_XAB6<
+ opcode, !or(xo, 0x20), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
+ !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
+ def PM#NAME#W :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, xo, (outs wacc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#WPP :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0x20), (outs acc:$AT),
+ !con((ins wacc:$ATi),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
}
// Defines 10 instructions, operand negating, unmasked, masked with 2, 4, 4
multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
string asmbase, string asmstr> {
defm NAME : ACC_UM_M244_XOEO<opcode, xo, IOL, asmbase, asmstr>;
- let Predicates = [MMA] in {
+ let Predicates = [MMA, IsNotISAFuture] in {
def PN : XX3Form_AT3_XAB6<
opcode, !or(xo, 0x80), (outs acc:$AT), !con((ins acc:$ATi), IOL),
!strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
!strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
- let Predicates = [MMA, PrefixInstrs] in {
+ let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
+ def WPN : XX3Form_AT3_XAB6<
+ opcode, !or(xo, 0x80), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
+ !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def WNP : XX3Form_AT3_XAB6<
+ opcode, !or(xo, 0x40), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
+ !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def WNN : XX3Form_AT3_XAB6<
+ opcode, !or(xo, 0xC0), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
+ !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+ let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PM#NAME#PN :
MMIRR_XX3Form_XY4P2_XAB6<
opcode, !or(xo, 0x80), (outs acc:$AT),
IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
+ def PM#NAME#WPN :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0x80), (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#WNP :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0x40), (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#WNN :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0xC0), (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
}
// Defines 5 instructions, unmasked, operand negating.
multiclass ACC_NEG_UM_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
string asmbase, string asmstr> {
defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
- let Predicates = [MMA] in {
+ let Predicates = [MMA, IsNotISAFuture] in {
def PN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs acc:$AT),
!con((ins acc:$ATi), IOL),
!strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
!strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+ let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
+ def WPN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs wacc:$AT),
+ !con((ins wacc:$ATi), IOL),
+ !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def WNP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs wacc:$AT),
+ !con((ins wacc:$ATi), IOL),
+ !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def WNN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs wacc:$AT),
+ !con((ins wacc:$ATi), IOL),
+ !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
}
// Defines 10 instructions, operand negating, unmasked, masked with 4, 4 bits.
multiclass ACC_NEG_UM_M44_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
string asmbase, string asmstr> {
defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;
- let Predicates = [MMA, PrefixInstrs] in {
+ let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PM#NAME :
MMIRR_XX3Form_XY4_XAB6<
opcode, !or(xo, 0x01), (outs acc:$AT),
IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
+ def PM#NAME#W :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, !or(xo, 0x01), (outs wacc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#WPP :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, xo, (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#WPN :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, !or(xo, 0x80), (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
+ !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#WNP :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, !or(xo, 0x40), (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
+ !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#WNN :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, !or(xo, 0xC0), (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
+ !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
}
// Defines 10 instructions, operand negating, unmasked, masked with 4, 2 bits.
multiclass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
string asmbase, string asmstr> {
defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;
- let Predicates = [MMA, PrefixInstrs] in {
+ let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PM#NAME :
MMIRR_XX3Form_X4Y2_XAB6<
opcode, !or(xo, 0x01), (outs acc:$AT),
IIC_VecFP, []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
+ def PM#NAME#W :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, !or(xo, 0x01), (outs wacc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#WPP :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, xo, (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#WPN :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, !or(xo, 0x80), (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
+ !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#WNP :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, !or(xo, 0x40), (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
+ !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#WNN :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, !or(xo, 0xC0), (outs wacc:$AT),
+ !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
+ !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
}
// End of class definitions.
//-----------------------------------------------------------------------------
-let Predicates = [MMA] in {
+let Predicates = [MMA, IsNotISAFuture] in {
def XXMFACC :
XForm_AT3<31, 0, 177, (outs acc:$ASo), (ins acc:$AS), "xxmfacc $AS",
IIC_VecGeneral,
}
}
-let Predicates = [MMA, PrefixInstrs] in {
+let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
+ // For Future and up XXMFACCW and XXMTACCW will not have patterns.
+ // On Future CPU the wacc registers no longer overlap with the vsr registers
+ // and so register allocation would have to know to match 4 vsr registers
+ // with one wacc register.
+ // On top of that Future CPU has a more convenient way to move between vsrs
+ // and wacc registers using xxextfdmr512 and xxinstdmr512.
+ def XXMFACCW :
+ XForm_AT3<31, 0, 177, (outs wacc:$ASo), (ins wacc:$AS), "xxmfacc $AS",
+ IIC_VecGeneral, []>,
+ RegConstraint<"$ASo = $AS">, NoEncode<"$ASo">;
+ def XXMTACCW :
+ XForm_AT3<31, 1, 177, (outs wacc:$AT), (ins wacc:$ATi), "xxmtacc $AT",
+ IIC_VecGeneral, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+
+ let isAsCheapAsAMove = 1, isReMaterializable = 1 in {
+ def XXSETACCZW :
+ XForm_AT3<31, 3, 177, (outs wacc:$AT), (ins), "xxsetaccz $AT",
+ IIC_VecGeneral, [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>;
+ }
+
+ def XVI8GER4WSPP :
+ XX3Form_AT3_XAB6<59, 99, (outs wacc:$AT),
+ (ins wacc:$ATi, vsrc:$XA, vsrc:$XB),
+ "xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+
+ let mayStore = 1 in {
+ def SPILL_WACC: PPCEmitTimePseudo<(outs), (ins wacc:$AT, memrix16:$dst),
+ "#SPILL_WACC", []>;
+ }
+ let mayLoad = 1, hasSideEffects = 0 in {
+ def RESTORE_WACC: PPCEmitTimePseudo<(outs wacc:$AT), (ins memrix16:$src),
+ "#RESTORE_WACC", []>;
+ }
+}
+
+let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PMXVI8GER4SPP :
MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs acc:$AT),
(ins acc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
+ def PMXVI8GER4WSPP :
+ MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs wacc:$AT),
+ (ins wacc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK,
+ u4imm:$YMSK, u4imm:$PMSK),
+ "pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK",
+ IIC_VecGeneral, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+}
+
// MMA accumulating/non-accumulating instructions.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// MMA Intrinsics
-let Predicates = [MMA] in {
+let Predicates = [MMA, IsNotISAFuture] in {
def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)),
(XVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC)>;
def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
(XVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC)>;
def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
(XVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+}
+let Predicates = [MMA, IsISAFuture] in {
+ def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)),
+ (XVI4GER8W RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVI4GER8WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+
+ def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)),
+ (XVI8GER4W RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVI8GER4WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+
+ def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)),
+ (XVI16GER2SW RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVI16GER2SWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+}
+
+let Predicates = [MMA, IsNotISAFuture] in {
def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)),
(XVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;
def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
(XVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
def : Pat<(v512i1 (int_ppc_mma_xvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
(XVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+}
+let Predicates = [MMA, IsISAFuture] in {
+ def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)),
+ (XVF16GER2W RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+}
+
+let Predicates = [MMA, IsNotISAFuture] in {
def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)),
(XVF32GER RCCp.AToVSRC, RCCp.BToVSRC)>;
def : Pat<(v512i1 (int_ppc_mma_xvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
(XVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
}
+let Predicates = [MMA, IsISAFuture] in {
+ def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)),
+ (XVF32GERW RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVF32GERWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVF32GERWPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVF32GERWNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVF32GERWNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf64ger v256i1:$XA, v16i8:$XB)),
+ (XVF64GERW $XA, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
+ (XVF64GERWPP $ATi, $XA, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
+ (XVF64GERWPN $ATi, $XA, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
+ (XVF64GERNP $ATi, $XA, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
+ (XVF64GERWNN $ATi, $XA, RCCp.BToVSRC)>;
+
+ def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2 v16i8:$XA, v16i8:$XB)),
+ (XVBF16GER2W RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVBF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVBF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVBF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVBF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvi16ger2 v16i8:$XA, v16i8:$XB)),
+ (XVI16GER2W RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVI16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+ def : Pat<(v512i1 (int_ppc_mma_xvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
+ (XVI8GER4WSPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
+}
// MMA Intrinsics
-let Predicates = [MMA, PrefixInstrs] in {
+
+let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
Msk4Imm:$YMSK, Msk8Imm:$PMSK)),
(PMXVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
}
+let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
+ def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk8Imm:$PMSK)),
+ (PMXVI4GER8W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk8Imm:$PMSK)),
+ (PMXVI4GER8WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;
+
+ def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
+ (PMXVI8GER4W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk4Imm:$PMSK)),
+ (PMXVI8GER4WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
+
+ def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2s v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
+ (PMXVI16GER2SW RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVI16GER2SWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
+ (PMXVF16GER2W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf32ger v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK)),
+ (PMXVF32GERW RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
+ (PMXVF32GERWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
+ (PMXVF32GERWPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
+ (PMXVF32GERWNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
+ (PMXVF32GERWNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK)>;
+
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf64ger v256i1:$XA, v16i8:$XB, Msk4Imm:$XMSK,
+ Msk2Imm:$YMSK)),
+ (PMXVF64GERW $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, Msk2Imm:$YMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
+ (PMXVF64GERWPP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk2Imm:$YMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
+ (PMXVF64GERWPN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk2Imm:$YMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
+ (PMXVF64GERWNP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk2Imm:$YMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
+ (PMXVF64GERWNN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk2Imm:$YMSK)>;
+
+ def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
+ (PMXVBF16GER2W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVBF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVBF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVBF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVBF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
+ (PMXVI16GER2W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVI8GER4WSPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
+ Msk4Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)),
+ (PMXVI16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+}
+
def ConcatsMMA {
dag VecsToVecPair0 =
(v256i1 (INSERT_SUBREG
dag Vec3 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx1));
}
-let Predicates = [MMA] in {
+let Predicates = [MMA, IsNotISAFuture] in {
def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
(XXMTACC ConcatsMMA.VecsToVecQuad)>;
def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
Extracts.Vec3>;
}
-
+let Predicates = [MMA, IsISAFuture] in {
+ def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
+ (DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
+ def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
+ v16i8:$vs3, v16i8:$vs2)),
+ (DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
+ def : Pat<(v512i1 immAllZerosV), (XXSETACCZW)>;
+}
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; This test is a copy of mma-intrinsics.ll except that it uses mcpu=future.
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=future -ppc-asm-full-reg-names \
+; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=future -ppc-asm-full-reg-names \
+; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=future -ppc-asm-full-reg-names \
+; RUN: -ppc-vsr-nums-as-vr -O0 < %s | FileCheck %s --check-prefix=CHECK-O0
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=future -ppc-asm-full-reg-names \
+; RUN: -ppc-vsr-nums-as-vr -O0 < %s | FileCheck %s --check-prefix=CHECK-O0-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix- \
+; RUN: -mcpu=future -vec-extabi \
+; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix- \
+; RUN: -mcpu=future -vec-extabi \
+; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX32
+
+; TODO: This test is missing some of the tests from mma-intrinsics.ll because
+; those tests do not work for mcpu=future. Once the fixes are in they
+; should be added back to this file.
+
+; assemble_acc
+declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: ass_acc:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmr v3, v2
+; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
+; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: stxv v4, 48(r3)
+; CHECK-NEXT: stxv v5, 32(r3)
+; CHECK-NEXT: stxv v2, 16(r3)
+; CHECK-NEXT: stxv v3, 0(r3)
+; CHECK-NEXT: blr
+;
+; CHECK-BE-LABEL: ass_acc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: vmr v3, v2
+; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: stxv v5, 48(r3)
+; CHECK-BE-NEXT: stxv v4, 32(r3)
+; CHECK-BE-NEXT: stxv v3, 16(r3)
+; CHECK-BE-NEXT: stxv v2, 0(r3)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-O0-LABEL: ass_acc:
+; CHECK-O0: # %bb.0: # %entry
+; CHECK-O0-NEXT: vmr v4, v2
+; CHECK-O0-NEXT: # implicit-def: $vsrp17
+; CHECK-O0-NEXT: vmr v3, v4
+; CHECK-O0-NEXT: vmr v2, v4
+; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
+; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-NEXT: xxlor vs0, v4, v4
+; CHECK-O0-NEXT: stxv vs0, 48(r3)
+; CHECK-O0-NEXT: xxlor vs0, v5, v5
+; CHECK-O0-NEXT: stxv vs0, 32(r3)
+; CHECK-O0-NEXT: xxlor vs0, v2, v2
+; CHECK-O0-NEXT: stxv vs0, 16(r3)
+; CHECK-O0-NEXT: xxlor vs0, v3, v3
+; CHECK-O0-NEXT: stxv vs0, 0(r3)
+; CHECK-O0-NEXT: blr
+;
+; CHECK-O0-BE-LABEL: ass_acc:
+; CHECK-O0-BE: # %bb.0: # %entry
+; CHECK-O0-BE-NEXT: vmr v4, v2
+; CHECK-O0-BE-NEXT: # implicit-def: $vsrp17
+; CHECK-O0-BE-NEXT: vmr v3, v4
+; CHECK-O0-BE-NEXT: vmr v2, v4
+; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
+; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
+; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)
+; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
+; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)
+; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
+; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)
+; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
+; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
+; CHECK-O0-BE-NEXT: blr
+;
+; CHECK-AIX64-LABEL: ass_acc:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT: vmr 3, 2
+; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 34, 34, 0
+; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX64-NEXT: stxv 5, 48(3)
+; CHECK-AIX64-NEXT: stxv 4, 32(3)
+; CHECK-AIX64-NEXT: stxv 3, 16(3)
+; CHECK-AIX64-NEXT: stxv 2, 0(3)
+; CHECK-AIX64-NEXT: blr
+;
+; CHECK-AIX32-LABEL: ass_acc:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT: vmr 3, 2
+; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 34, 34, 0
+; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX32-NEXT: stxv 5, 48(3)
+; CHECK-AIX32-NEXT: stxv 4, 32(3)
+; CHECK-AIX32-NEXT: stxv 3, 16(3)
+; CHECK-AIX32-NEXT: stxv 2, 0(3)
+; CHECK-AIX32-NEXT: blr
+entry:
+ %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
+ store <512 x i1> %0, ptr %ptr, align 64
+ ret void
+}
+
+; xxsetaccz
+declare <512 x i1> @llvm.ppc.mma.xxsetaccz()
+define void @int_xxsetaccz(ptr %ptr) {
+; CHECK-LABEL: int_xxsetaccz:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxsetaccz wacc0
+; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: stxv v4, 48(r3)
+; CHECK-NEXT: stxv v5, 32(r3)
+; CHECK-NEXT: stxv v2, 16(r3)
+; CHECK-NEXT: stxv v3, 0(r3)
+; CHECK-NEXT: blr
+;
+; CHECK-BE-LABEL: int_xxsetaccz:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xxsetaccz wacc0
+; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: stxv v5, 48(r3)
+; CHECK-BE-NEXT: stxv v4, 32(r3)
+; CHECK-BE-NEXT: stxv v3, 16(r3)
+; CHECK-BE-NEXT: stxv v2, 0(r3)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-O0-LABEL: int_xxsetaccz:
+; CHECK-O0: # %bb.0: # %entry
+; CHECK-O0-NEXT: xxsetaccz wacc0
+; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-NEXT: xxlor vs0, v4, v4
+; CHECK-O0-NEXT: stxv vs0, 48(r3)
+; CHECK-O0-NEXT: xxlor vs0, v5, v5
+; CHECK-O0-NEXT: stxv vs0, 32(r3)
+; CHECK-O0-NEXT: xxlor vs0, v2, v2
+; CHECK-O0-NEXT: stxv vs0, 16(r3)
+; CHECK-O0-NEXT: xxlor vs0, v3, v3
+; CHECK-O0-NEXT: stxv vs0, 0(r3)
+; CHECK-O0-NEXT: blr
+;
+; CHECK-O0-BE-LABEL: int_xxsetaccz:
+; CHECK-O0-BE: # %bb.0: # %entry
+; CHECK-O0-BE-NEXT: xxsetaccz wacc0
+; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
+; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)
+; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
+; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)
+; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
+; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)
+; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
+; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
+; CHECK-O0-BE-NEXT: blr
+;
+; CHECK-AIX64-LABEL: int_xxsetaccz:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT: xxsetaccz 0
+; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX64-NEXT: stxv 5, 48(3)
+; CHECK-AIX64-NEXT: stxv 4, 32(3)
+; CHECK-AIX64-NEXT: stxv 3, 16(3)
+; CHECK-AIX64-NEXT: stxv 2, 0(3)
+; CHECK-AIX64-NEXT: blr
+;
+; CHECK-AIX32-LABEL: int_xxsetaccz:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT: xxsetaccz 0
+; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX32-NEXT: stxv 5, 48(3)
+; CHECK-AIX32-NEXT: stxv 4, 32(3)
+; CHECK-AIX32-NEXT: stxv 3, 16(3)
+; CHECK-AIX32-NEXT: stxv 2, 0(3)
+; CHECK-AIX32-NEXT: blr
+entry:
+ %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
+ store <512 x i1> %0, ptr %ptr, align 64
+ ret void
+}
+
+; disassemble_acc
+declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
+define void @disass_acc(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {
+; CHECK-LABEL: disass_acc:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxsetaccz wacc0
+; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: stxv v5, 0(r3)
+; CHECK-NEXT: stxv v4, 0(r4)
+; CHECK-NEXT: stxv v3, 0(r5)
+; CHECK-NEXT: stxv v2, 0(r6)
+; CHECK-NEXT: blr
+;
+; CHECK-BE-LABEL: disass_acc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xxsetaccz wacc0
+; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: stxv v2, 0(r3)
+; CHECK-BE-NEXT: stxv v3, 0(r4)
+; CHECK-BE-NEXT: stxv v4, 0(r5)
+; CHECK-BE-NEXT: stxv v5, 0(r6)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-O0-LABEL: disass_acc:
+; CHECK-O0: # %bb.0: # %entry
+; CHECK-O0-NEXT: xxsetaccz wacc0
+; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp32, vsp36, 0
+; CHECK-O0-NEXT: vmr v2, v0
+; CHECK-O0-NEXT: xxlor vs0, v1, v1
+; CHECK-O0-NEXT: xxlor vs1, v4, v4
+; CHECK-O0-NEXT: xxlor vs2, v5, v5
+; CHECK-O0-NEXT: stxv vs2, 0(r3)
+; CHECK-O0-NEXT: stxv vs1, 0(r4)
+; CHECK-O0-NEXT: stxv vs0, 0(r5)
+; CHECK-O0-NEXT: stxv v2, 0(r6)
+; CHECK-O0-NEXT: blr
+;
+; CHECK-O0-BE-LABEL: disass_acc:
+; CHECK-O0-BE: # %bb.0: # %entry
+; CHECK-O0-BE-NEXT: xxsetaccz wacc0
+; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp36, vsp32, 0
+; CHECK-O0-BE-NEXT: vmr v2, v1
+; CHECK-O0-BE-NEXT: xxlor vs0, v0, v0
+; CHECK-O0-BE-NEXT: xxlor vs1, v5, v5
+; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4
+; CHECK-O0-BE-NEXT: stxv vs2, 0(r3)
+; CHECK-O0-BE-NEXT: stxv vs1, 0(r4)
+; CHECK-O0-BE-NEXT: stxv vs0, 0(r5)
+; CHECK-O0-BE-NEXT: stxv v2, 0(r6)
+; CHECK-O0-BE-NEXT: blr
+;
+; CHECK-AIX64-LABEL: disass_acc:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT: xxsetaccz 0
+; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX64-NEXT: stxv 2, 0(3)
+; CHECK-AIX64-NEXT: stxv 3, 0(4)
+; CHECK-AIX64-NEXT: stxv 4, 0(5)
+; CHECK-AIX64-NEXT: stxv 5, 0(6)
+; CHECK-AIX64-NEXT: blr
+;
+; CHECK-AIX32-LABEL: disass_acc:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT: xxsetaccz 0
+; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX32-NEXT: stxv 2, 0(3)
+; CHECK-AIX32-NEXT: stxv 3, 0(4)
+; CHECK-AIX32-NEXT: stxv 4, 0(5)
+; CHECK-AIX32-NEXT: stxv 5, 0(6)
+; CHECK-AIX32-NEXT: blr
+entry:
+ %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
+ %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
+ %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
+ %3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
+ %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
+ %5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
+ store <16 x i8> %2, ptr %ptr1, align 16
+ store <16 x i8> %3, ptr %ptr2, align 16
+ store <16 x i8> %4, ptr %ptr3, align 16
+ store <16 x i8> %5, ptr %ptr4, align 16
+ ret void
+}
+
+declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>)
+declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>)
+declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)
+
+define void @testcse(ptr %res, <16 x i8> %vc) {
+; CHECK-LABEL: testcse:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxsetaccz wacc0
+; CHECK-NEXT: xvf32gerpp wacc0, v2, v2
+; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: stxv v4, 48(r3)
+; CHECK-NEXT: stxv v5, 32(r3)
+; CHECK-NEXT: stxv v2, 16(r3)
+; CHECK-NEXT: stxv v3, 0(r3)
+; CHECK-NEXT: stxv v4, 112(r3)
+; CHECK-NEXT: stxv v5, 96(r3)
+; CHECK-NEXT: stxv v2, 80(r3)
+; CHECK-NEXT: stxv v3, 64(r3)
+; CHECK-NEXT: blr
+;
+; CHECK-BE-LABEL: testcse:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xxsetaccz wacc0
+; CHECK-BE-NEXT: xvf32gerpp wacc0, v2, v2
+; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: stxv v5, 48(r3)
+; CHECK-BE-NEXT: stxv v4, 32(r3)
+; CHECK-BE-NEXT: stxv v3, 16(r3)
+; CHECK-BE-NEXT: stxv v2, 0(r3)
+; CHECK-BE-NEXT: stxv v5, 112(r3)
+; CHECK-BE-NEXT: stxv v4, 96(r3)
+; CHECK-BE-NEXT: stxv v3, 80(r3)
+; CHECK-BE-NEXT: stxv v2, 64(r3)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-O0-LABEL: testcse:
+; CHECK-O0: # %bb.0: # %entry
+; CHECK-O0-NEXT: xxsetaccz wacc0
+; CHECK-O0-NEXT: xvf32gerpp wacc0, v2, v2
+; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-NEXT: xxlor vs3, v4, v4
+; CHECK-O0-NEXT: stxv vs3, 48(r3)
+; CHECK-O0-NEXT: xxlor vs2, v5, v5
+; CHECK-O0-NEXT: stxv vs2, 32(r3)
+; CHECK-O0-NEXT: xxlor vs1, v2, v2
+; CHECK-O0-NEXT: stxv vs1, 16(r3)
+; CHECK-O0-NEXT: xxlor vs0, v3, v3
+; CHECK-O0-NEXT: stxv vs0, 0(r3)
+; CHECK-O0-NEXT: stxv vs3, 112(r3)
+; CHECK-O0-NEXT: stxv vs2, 96(r3)
+; CHECK-O0-NEXT: stxv vs1, 80(r3)
+; CHECK-O0-NEXT: stxv vs0, 64(r3)
+; CHECK-O0-NEXT: blr
+;
+; CHECK-O0-BE-LABEL: testcse:
+; CHECK-O0-BE: # %bb.0: # %entry
+; CHECK-O0-BE-NEXT: xxsetaccz wacc0
+; CHECK-O0-BE-NEXT: xvf32gerpp wacc0, v2, v2
+; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-BE-NEXT: xxlor vs3, v5, v5
+; CHECK-O0-BE-NEXT: stxv vs3, 48(r3)
+; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4
+; CHECK-O0-BE-NEXT: stxv vs2, 32(r3)
+; CHECK-O0-BE-NEXT: xxlor vs1, v3, v3
+; CHECK-O0-BE-NEXT: stxv vs1, 16(r3)
+; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
+; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
+; CHECK-O0-BE-NEXT: stxv vs3, 112(r3)
+; CHECK-O0-BE-NEXT: stxv vs2, 96(r3)
+; CHECK-O0-BE-NEXT: stxv vs1, 80(r3)
+; CHECK-O0-BE-NEXT: stxv vs0, 64(r3)
+; CHECK-O0-BE-NEXT: blr
+;
+; CHECK-AIX64-LABEL: testcse:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT: xxsetaccz 0
+; CHECK-AIX64-NEXT: xvf32gerpp 0, 2, 2
+; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX64-NEXT: stxv 5, 48(3)
+; CHECK-AIX64-NEXT: stxv 4, 32(3)
+; CHECK-AIX64-NEXT: stxv 3, 16(3)
+; CHECK-AIX64-NEXT: stxv 2, 0(3)
+; CHECK-AIX64-NEXT: stxv 5, 112(3)
+; CHECK-AIX64-NEXT: stxv 4, 96(3)
+; CHECK-AIX64-NEXT: stxv 3, 80(3)
+; CHECK-AIX64-NEXT: stxv 2, 64(3)
+; CHECK-AIX64-NEXT: blr
+;
+; CHECK-AIX32-LABEL: testcse:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT: xxsetaccz 0
+; CHECK-AIX32-NEXT: xvf32gerpp 0, 2, 2
+; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX32-NEXT: stxv 5, 48(3)
+; CHECK-AIX32-NEXT: stxv 4, 32(3)
+; CHECK-AIX32-NEXT: stxv 3, 16(3)
+; CHECK-AIX32-NEXT: stxv 2, 0(3)
+; CHECK-AIX32-NEXT: stxv 5, 112(3)
+; CHECK-AIX32-NEXT: stxv 4, 96(3)
+; CHECK-AIX32-NEXT: stxv 3, 80(3)
+; CHECK-AIX32-NEXT: stxv 2, 64(3)
+; CHECK-AIX32-NEXT: blr
+entry:
+ %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
+ %1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
+ %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
+ %3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
+ %4 = getelementptr inbounds <512 x i1>, ptr %res, i64 0
+ %5 = getelementptr inbounds <512 x i1>, ptr %res, i64 1
+ store <512 x i1> %2, ptr %4, align 64
+ store <512 x i1> %3, ptr %5, align 64
+ ret void
+}