[Hexagon] Rearrange bits in TSFlags, NFC

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
index 898ef51..ee72d34 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
@@ -134,37 +134,37 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
 
   // Addressing mode for load/store instructions.
   AddrModeType addrMode = NoAddrMode;
-  let TSFlags{44-42} = addrMode.Value;
+  let TSFlags{42-40} = addrMode.Value;
 
   // Memory access size for mem access instructions (load/store)
   MemAccessSize accessSize = NoMemAccess;
-  let TSFlags{48-45} = accessSize.Value;
+  let TSFlags{46-43} = accessSize.Value;
 
   bits<1> isTaken = 0;
-  let TSFlags {49} = isTaken; // Branch prediction.
+  let TSFlags {47} = isTaken; // Branch prediction.
 
   bits<1> isFP = 0;
-  let TSFlags {50} = isFP; // Floating-point.
+  let TSFlags {48} = isFP; // Floating-point.
 
   bits<1> hasNewValue2 = 0;
-  let TSFlags{52} = hasNewValue2; // Second New-value producer insn.
+  let TSFlags{50} = hasNewValue2; // Second New-value producer insn.
   bits<3> opNewValue2 = 0;
-  let TSFlags{55-53} = opNewValue2; // Second New-value produced operand.
+  let TSFlags{53-51} = opNewValue2; // Second New-value produced operand.
 
   bits<1> isAccumulator = 0;
-  let TSFlags{56} = isAccumulator;
+  let TSFlags{54} = isAccumulator;
 
   bits<1> prefersSlot3 = 0;
-  let TSFlags{57} = prefersSlot3; // Complex XU
+  let TSFlags{55} = prefersSlot3; // Complex XU
 
   bits<1> hasHvxTmp = 0;
-  let TSFlags{60} = hasHvxTmp;  // vector register vX.tmp false-write
+  let TSFlags{56} = hasHvxTmp;  // vector register vX.tmp false-write
 
   bit CVINew = 0;
-  let TSFlags{62} = CVINew;
+  let TSFlags{58} = CVINew;
 
   bit isCVI = 0;
-  let TSFlags{63} = isCVI;
+  let TSFlags{59} = isCVI;
 
   // Fields used for relation models.
   bit isNonTemporal = 0;
@@ -265,8 +265,8 @@ class OpcodeDuplex {
   let Inst{12-0}  = ISubLo;
 }
 
-class InstDuplex<bits<4> iClass, string cstr = "">
-  : Instruction, OpcodeDuplex {
+class InstDuplex<bits<4> iClass, string cstr = ""> : Instruction,
+                                                     OpcodeDuplex {
   let Namespace = "Hexagon";
   IType Type = TypeDUPLEX;  // uses slot 0,1
   let isCodeGenOnly = 1;

diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
index c9a1781..78fa195 100644 (file)
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
@@ -125,42 +125,42 @@ namespace HexagonII {
     RestrictNoSlot1StoreMask = 0x1,
 
     // Addressing mode for load/store instructions.
-    AddrModePos = 42,
+    AddrModePos = 40,
     AddrModeMask = 0x7,
     // Access size for load/store instructions.
-    MemAccessSizePos = 45,
+    MemAccessSizePos = 43,
     MemAccesSizeMask = 0xf,
 
     // Branch predicted taken.
-    TakenPos = 49,
+    TakenPos = 47,
     TakenMask = 0x1,
 
     // Floating-point instructions.
-    FPPos = 50,
+    FPPos = 48,
     FPMask = 0x1,
 
     // New-Value producer-2 instructions.
-    hasNewValuePos2 = 52,
+    hasNewValuePos2 = 50,
     hasNewValueMask2 = 0x1,
     // Which operand consumes or produces a new value.
-    NewValueOpPos2 = 53,
+    NewValueOpPos2 = 51,
     NewValueOpMask2 = 0x7,
 
     // Accumulator instructions.
-    AccumulatorPos = 56,
+    AccumulatorPos = 54,
     AccumulatorMask = 0x1,
 
     // Complex XU, prevent xu competition by preferring slot3
-    PrefersSlot3Pos = 57,
+    PrefersSlot3Pos = 55,
     PrefersSlot3Mask = 0x1,
 
-    HasHvxTmpPos = 60,
+    HasHvxTmpPos = 56,
     HasHvxTmpMask = 0x1,
 
-    CVINewPos = 62,
+    CVINewPos = 58,
     CVINewMask = 0x1,
 
-    isCVIPos = 63,
+    isCVIPos = 59,
     isCVIMask = 0x1,
   };