clk: at91: sama7g5: fix parents of PDMCs' GCLK

Audio PLL can be used as parent by the GCLKs of PDMCs.

Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220304182616.1920392-1-codrin.ciubotariu@microchip.com

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index e434586..9a213ba 100644 (file)
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -699,16 +699,16 @@ static const struct {
        { .n  = "pdmc0_gclk",
          .id = 68,
          .r = { .max = 50000000  },
-         .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
-         .pp_mux_table = { 5, 8, },
+         .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
+         .pp_mux_table = { 5, 9, },
          .pp_count = 2,
          .pp_chg_id = INT_MIN, },
 
        { .n  = "pdmc1_gclk",
          .id = 69,
          .r = { .max = 50000000, },
-         .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
-         .pp_mux_table = { 5, 8, },
+         .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
+         .pp_mux_table = { 5, 9, },
          .pp_count = 2,
          .pp_chg_id = INT_MIN, },