radv: allow DGC on the compute queue

DGC cmdbuf on ACE are executed as IB1 without chaining because IB2
isn't supported on ACE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index c4085b74755a8c74db21abcd173f25533f4d8851..0529c9f80eaab3316d4c7a018e4fd971c7f8f0eb 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -9470,10 +9470,6 @@ radv_CmdExecuteGeneratedCommandsNV(VkCommandBuffer commandBuffer, VkBool32 isPre
    const bool compute = layout->pipeline_bind_point == VK_PIPELINE_BIND_POINT_COMPUTE;
    const struct radv_device *device = cmd_buffer->device;
 
-   /* The only actions that can be done are draws, so skip on other queues. */
-   if (cmd_buffer->qf != RADV_QUEUE_GENERAL)
-      return;
-
    /* Secondary command buffers are needed for the full extension but can't use
     * PKT3_INDIRECT_BUFFER.
     */
@@ -9505,8 +9501,10 @@ radv_CmdExecuteGeneratedCommandsNV(VkCommandBuffer commandBuffer, VkBool32 isPre
    const uint64_t ib_offset = prep_buffer->offset + pGeneratedCommandsInfo->preprocessOffset;
    const uint32_t view_mask = cmd_buffer->state.render.view_mask;
 
-   radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
-   radeon_emit(cmd_buffer->cs, 0);
+   if (!radv_cmd_buffer_uses_mec(cmd_buffer)) {
+      radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
+      radeon_emit(cmd_buffer->cs, 0);
+   }
 
    if (compute || !view_mask) {
       device->ws->cs_execute_ib(cmd_buffer->cs, ib_bo, ib_offset, cmdbuf_size >> 2);