[X86] Weaken an overly aggressive assert.

This assert tried to check that AND constants are only on the RHS. But its possible for both operands to be constants if one is opaque which will prevent the AND from being constant folded.

Fixes PR38771

llvm-svn: 341102

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 3c01c32..6326067 100644 (file)
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18035,7 +18035,13 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl,
         if (!ZeroCheck)
           break;
 
-        assert(!isa<ConstantSDNode>(Op0) && "AND node isn't canonicalized");
+        // And with cosntant should be canonicalized unless we're dealing
+        // with opaque constants.
+        assert((!isa<ConstantSDNode>(Op0) ||
+                (isa<ConstantSDNode>(Op1) &&
+                 (cast<ConstantSDNode>(Op0)->isOpaque() ||
+                  cast<ConstantSDNode>(Op1)->isOpaque()))) &&
+               "AND node isn't canonicalized");
         auto *CN = dyn_cast<ConstantSDNode>(Op1);
         if (!CN)
           break;

diff --git a/llvm/test/CodeGen/X86/pr38771.ll b/llvm/test/CodeGen/X86/pr38771.ll
new file mode 100644 (file)
index 0000000..2a9ee66
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr38771.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define void @function() nounwind {
+; CHECK-LABEL: function:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movabsq $281474976710656, %rax # imm = 0x1000000000000
+; CHECK-NEXT:    notq %rax
+; CHECK-NEXT:    movl $2147483647, %ecx # imm = 0x7FFFFFFF
+; CHECK-NEXT:    shldq $65, %rax, %rcx
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    movb $64, %dl
+; CHECK-NEXT:    testb %dl, %dl
+; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    movq %rax, (%rax)
+; CHECK-NEXT:    movl $0, (%rax)
+; CHECK-NEXT:    retq
+entry:
+  %B68 = sub i96 39614081257132168796771975167, 281474976710656
+  %B49 = or i96 39614081257132168796771975167, 39614081257132168796771975167
+  %B33 = lshr i96 %B68, %B68
+  store i96 %B33, i96* undef
+  ret void
+}