drm/i915/gvt: make width of mmio_attribute bigger
authorYan Zhao <yan.y.zhao@intel.com>
Wed, 23 Dec 2020 03:45:45 +0000 (11:45 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Fri, 25 Dec 2020 03:16:14 +0000 (11:16 +0800)
8 bits are all used up. extend it to 16 bits to hold more flags.

Suggested-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20201223034545.17224-1-yan.y.zhao@intel.com
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/gvt.h
drivers/gpu/drm/i915/gvt/handlers.c

index 3e268e2..f82ad5a 100644 (file)
@@ -244,7 +244,7 @@ struct gvt_mmio_block {
 #define INTEL_GVT_MMIO_HASH_BITS 11
 
 struct intel_gvt_mmio {
-       u8 *mmio_attribute;
+       u16 *mmio_attribute;
 /* Register contains RO bits */
 #define F_RO           (1 << 0)
 /* Register contains graphics address */
index 7012e4c..bc3d28f 100644 (file)
@@ -96,7 +96,7 @@ struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
 }
 
 static int new_mmio_info(struct intel_gvt *gvt,
-               u32 offset, u8 flags, u32 size,
+               u32 offset, u16 flags, u32 size,
                u32 addr_mask, u32 ro_mask, u32 device,
                gvt_mmio_func read, gvt_mmio_func write)
 {