Remove <undef> from rematerialized full register

When coalescing a small register into a subregister of a larger register,
if the larger register is rematerialized, the function updateRegDefUses
can add an <undef> flag to the rematerialized definition (since it's
treating it as only definining the coalesced subregister). While with that
assumption doing so is not incorrect, make sure to remove the flag later
on after the call to updateRegDefUses.

llvm-svn: 334845

diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index db5258e..20e38f2 100644 (file)
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1231,6 +1231,11 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
     // Update machine operands and add flags.
     updateRegDefsUses(DstReg, DstReg, DstIdx);
     NewMI.getOperand(0).setSubReg(NewIdx);
+    // updateRegDefUses can add an "undef" flag to the definition, since
+    // it will replace DstReg with DstReg.DstIdx. If NewIdx is 0, make
+    // sure that "undef" is not set.
+    if (NewIdx == 0)
+      NewMI.getOperand(0).setIsUndef(false);
     // Add dead subregister definitions if we are defining the whole register
     // but only part of it is live.
     // This could happen if the rematerialization instruction is rematerializing

diff --git a/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir
new file mode 100644 (file)
index 0000000..8fcac5d
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir
@@ -0,0 +1,37 @@
+# RUN: llc -march=hexagon -run-pass=simple-register-coalescing -o - %s | FileCheck %s
+
+# Make sure that the coalescer does not create a full definition with
+# an undef flag on the destination. This used to happen when rematerializing
+# a double register and coalescing a smaller reg into a subreg of it.
+
+# CHECK-NOT: undef %[0-9]+:doubleregs = A2_tfrpi 1
+
+---
+name: fred
+tracksRegLiveness: true
+body: |
+
+  bb.0:
+    successors: %bb.1(0x80000000); %bb.1(200.00%)
+
+    %18:doubleregs = A2_tfrpi 1
+    %23:intregs = IMPLICIT_DEF
+    %24:doubleregs = IMPLICIT_DEF
+
+  bb.1:
+    successors: %bb.1(0x80000000); %bb.1(200.00%)
+
+    %1:doubleregs = COPY %24:doubleregs
+    %0:intregs = COPY %23:intregs
+    %13:intregs = COPY %18.isub_lo:doubleregs
+    %13:intregs = S2_asl_i_r_or %13:intregs, %0:intregs, 1
+    %15:intregs = S2_extractu %0:intregs, 1, 31
+    undef %17.isub_lo:doubleregs = COPY %13:intregs
+    %17.isub_hi:doubleregs = COPY %15:intregs
+    %2:doubleregs = A2_addp %17:doubleregs, %1:doubleregs
+    %3:intregs = A2_addi %0:intregs, -1
+    %23:intregs = COPY %3:intregs
+    %24:doubleregs = COPY %2:doubleregs
+    J2_jump %bb.1, implicit-def dead $pc
+
+...