projects / platform / upstream / linaro-gcc.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 45d7e71)
* config/i386/sse.md (<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>):
authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 5 Sep 2012 15:20:01 +0000 (15:20 +0000)
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 5 Sep 2012 15:20:01 +0000 (15:20 +0000)
Use register_operand instead of reg_not_xmm0_operand{,_maybe_avx}.
Use nonimmediate_operand instead of
nonimm_not_xmm0_operand{,_maybe_avx}.
(<sse4_1_avx2>_pblendvb): Ditto.
(sse4_2_pcmpestr): Ditto.
(*sse4_2_pcmpestr_unaligned): Ditto.
(sse4_2_pcmpistr): Ditto.
(*sse4_2_pcmpistr_unaligned): Ditto.
* config/i386/predicates.md (reg_not_xmm0_operand): Remove predicate.
(nonimm_not_xmm0_operand): Ditto.
(nonimm_not_xmm0_operand_maybe_avx): Ditto.
(nonimm_not_xmm0_operand_maybe_avx): Ditto.
* config/i386/i386.md (rdpmc): Do not force operand 1 into ecx.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@190985 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog patch | blob | history
gcc/config/i386/i386.md patch | blob | history
gcc/config/i386/predicates.md patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index be43602..73e5f20 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2012-09-05  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/sse.md (<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>):
+       Use register_operand instead of reg_not_xmm0_operand{,_maybe_avx}.
+       Use nonimmediate_operand instead of
+       nonimm_not_xmm0_operand{,_maybe_avx}.
+       (<sse4_1_avx2>_pblendvb): Ditto.
+       (sse4_2_pcmpestr): Ditto.
+       (*sse4_2_pcmpestr_unaligned): Ditto.
+       (sse4_2_pcmpistr): Ditto.
+       (*sse4_2_pcmpistr_unaligned): Ditto.
+       * config/i386/predicates.md (reg_not_xmm0_operand): Remove predicate.
+       (nonimm_not_xmm0_operand): Ditto.
+       (nonimm_not_xmm0_operand_maybe_avx): Ditto.
+       (nonimm_not_xmm0_operand_maybe_avx): Ditto.
+       * config/i386/i386.md (rdpmc): Do not force operand 1 into ecx.
+
 2012-09-05  Eric Botcazou  <ebotcazou@adacore.com>
 
        * bb-reorder.c: Clarify a few points in the head comment and fix
@@ -217,8 +234,8 @@
 2012-09-04  Bin Cheng  <bin.cheng@arm.com>
 
        PR target/45070
-       * config/arm/arm.c (thumb1_extra_regs_pushed): Handle return value of size
-       less than 4 bytes by using macro ARM_NUM_INTS.
+       * config/arm/arm.c (thumb1_extra_regs_pushed): Handle return value
+       of size less than 4 bytes by using macro ARM_NUM_INTS.
        (thumb1_unexpanded_epilogue): Use macro ARM_NUM_INTS.
 
 2012-09-04  Richard Guenther  <rguenther@suse.de>
@@ -242,10 +259,8 @@
 
 2012-09-04  Christophe Lyon  <christophe.lyon@linaro.org>
 
-       * config/arm/arm.c (arm_evpc_neon_vext): New
-       function.
-       (arm_expand_vec_perm_const_1): Add call to
-       arm_evpc_neon_vext.
+       * config/arm/arm.c (arm_evpc_neon_vext): New function.
+       (arm_expand_vec_perm_const_1): Add call to arm_evpc_neon_vext.
 
 2012-09-04  Oleg Endo  <olegendo@gcc.gnu.org>
 
@@ -401,7 +416,7 @@
 2012-08-31  Greta Yorsh  <Greta.Yorsh@arm.com>
 
        * config/arm/arm.c (arm_expand_epilogue): Remove unused variable
-        floats_from_frame.
+       floats_from_frame.
 
 2012-08-31  Martin Jambor  <mjambor@suse.cz>
 
@@ -2634,11 +2649,6 @@
        (macro define __LINE__): New.
        (skip "tree.h"): New.
 
-2012-08-14  Uros Bizjak  <ubizjak@gmail.com>
-
-       * config/i386/i386.md (enabled): Add comment with explanation
-       why fma4 instructions are disabled for generic code.
-
 2012-08-14  Oleg Endo  <olegendo@gcc.gnu.org>
 
        PR target/52933
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 16cee7a..898e015 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -17983,10 +17983,7 @@
   rtx reg = gen_reg_rtx (DImode);
   rtx si;
 
-  /* Force operand 1 into ECX.  */
-  rtx ecx = gen_rtx_REG (SImode, CX_REG);
-  emit_insn (gen_rtx_SET (VOIDmode, ecx, operands[1]));
-  si = gen_rtx_UNSPEC_VOLATILE (DImode, gen_rtvec (1, ecx),
+  si = gen_rtx_UNSPEC_VOLATILE (DImode, gen_rtvec (1, operands[1]),
                                UNSPECV_RDPMC);
 
   if (TARGET_64BIT)
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 55e4b56..d4f40b1 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -93,33 +93,6 @@
        (match_test "TARGET_64BIT")
        (match_test "REGNO (op) > BX_REG")))
 
-;; Return true if op is not xmm0 register.
-(define_predicate "reg_not_xmm0_operand"
-  (match_operand 0 "register_operand")
-{
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  return !REG_P (op) || REGNO (op) != FIRST_SSE_REG;
-})
-
-;; As above, but also allow memory operands.
-(define_predicate "nonimm_not_xmm0_operand"
-  (ior (match_operand 0 "memory_operand")
-       (match_operand 0 "reg_not_xmm0_operand")))
-
-;; Return true if op is not xmm0 register, but only for non-AVX targets.
-(define_predicate "reg_not_xmm0_operand_maybe_avx"
-  (if_then_else (match_test "TARGET_AVX")
-    (match_operand 0 "register_operand")
-    (match_operand 0 "reg_not_xmm0_operand")))
-
-;; As above, but also allow memory operands.
-(define_predicate "nonimm_not_xmm0_operand_maybe_avx"
-  (if_then_else (match_test "TARGET_AVX")
-    (match_operand 0 "nonimmediate_operand")
-    (match_operand 0 "nonimm_not_xmm0_operand")))
-
 ;; Return true if VALUE can be stored in a sign extended immediate field.
 (define_predicate "x86_64_immediate_operand"
   (match_code "const_int,symbol_ref,label_ref,const")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 51d77e0..da8bc1e 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8593,10 +8593,10 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>"
-  [(set (match_operand:VF 0 "reg_not_xmm0_operand_maybe_avx" "=x,x")
+  [(set (match_operand:VF 0 "register_operand" "=x,x")
        (unspec:VF
-         [(match_operand:VF 1 "reg_not_xmm0_operand_maybe_avx" "0,x")
-          (match_operand:VF 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
+         [(match_operand:VF 1 "register_operand" "0,x")
+          (match_operand:VF 2 "nonimmediate_operand" "xm,xm")
           (match_operand:VF 3 "register_operand" "Yz,x")]
          UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
@@ -8691,10 +8691,10 @@
    (set_attr "mode" "TI")])
 
 (define_insn "<sse4_1_avx2>_pblendvb"
-  [(set (match_operand:VI1_AVX2 0 "reg_not_xmm0_operand" "=x,x")
+  [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x")
        (unspec:VI1_AVX2
-         [(match_operand:VI1_AVX2 1 "reg_not_xmm0_operand_maybe_avx"  "0,x")
-          (match_operand:VI1_AVX2 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
+         [(match_operand:VI1_AVX2 1 "register_operand"  "0,x")
+          (match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm")
           (match_operand:VI1_AVX2 3 "register_operand" "Yz,x")]
          UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
@@ -9164,9 +9164,9 @@
 (define_insn_and_split "sse4_2_pcmpestr"
   [(set (match_operand:SI 0 "register_operand" "=c,c")
        (unspec:SI
-         [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
+         [(match_operand:V16QI 2 "register_operand" "x,x")
           (match_operand:SI 3 "register_operand" "a,a")
-          (match_operand:V16QI 4 "nonimm_not_xmm0_operand" "x,m")
+          (match_operand:V16QI 4 "nonimmediate_operand" "x,m")
           (match_operand:SI 5 "register_operand" "d,d")
           (match_operand:SI 6 "const_0_to_255_operand" "n,n")]
          UNSPEC_PCMPESTR))
@@ -9224,7 +9224,7 @@
 (define_insn_and_split "*sse4_2_pcmpestr_unaligned"
   [(set (match_operand:SI 0 "register_operand" "=c")
        (unspec:SI
-         [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x")
+         [(match_operand:V16QI 2 "register_operand" "x")
           (match_operand:SI 3 "register_operand" "a")
           (unspec:V16QI
             [(match_operand:V16QI 4 "memory_operand" "m")]
@@ -9365,8 +9365,8 @@
 (define_insn_and_split "sse4_2_pcmpistr"
   [(set (match_operand:SI 0 "register_operand" "=c,c")
        (unspec:SI
-         [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
-          (match_operand:V16QI 3 "nonimm_not_xmm0_operand" "x,m")
+         [(match_operand:V16QI 2 "register_operand" "x,x")
+          (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
           (match_operand:SI 4 "const_0_to_255_operand" "n,n")]
          UNSPEC_PCMPISTR))
    (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
@@ -9416,7 +9416,7 @@
 (define_insn_and_split "*sse4_2_pcmpistr_unaligned"
   [(set (match_operand:SI 0 "register_operand" "=c")
        (unspec:SI
-         [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x")
+         [(match_operand:V16QI 2 "register_operand" "x")
           (unspec:V16QI
             [(match_operand:V16QI 3 "memory_operand" "m")]
             UNSPEC_MOVU)
Domain: System / Toolchain;