transfer->map = calloc(transfer->base.layer_stride, box->depth);
assert(box->depth == 1);
- if ((usage & PIPE_MAP_READ) && rsrc->slices[level].data_valid) {
+ if ((usage & PIPE_MAP_READ) && BITSET_TEST(rsrc->data_valid, level)) {
agx_detile(
((uint8_t *) bo->ptr.cpu) + rsrc->slices[level].offset,
transfer->map,
/* Be conservative for direct writes */
if ((usage & PIPE_MAP_WRITE) && (usage & PIPE_MAP_DIRECTLY))
- rsrc->slices[level].data_valid = true;
+ BITSET_SET(rsrc->data_valid, level);
return ((uint8_t *) bo->ptr.cpu)
+ rsrc->slices[level].offset
unsigned bytes_per_pixel = util_format_get_blocksize(prsrc->format);
if (transfer->usage & PIPE_MAP_WRITE)
- rsrc->slices[transfer->level].data_valid = true;
+ BITSET_SET(rsrc->data_valid, transfer->level);
/* Tiling will occur in software from a staging cpu buffer */
if ((transfer->usage & PIPE_MAP_WRITE) &&
memset(pipeline_null.cpu, 0, 64);
struct agx_resource *rt0 = agx_resource(ctx->batch->cbufs[0]->texture);
- rt0->slices[0].data_valid = true;
+ BITSET_SET(rt0->data_valid, 0);
/* BO list for a given batch consists of:
* - BOs for the batch's framebuffer surfaces