clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate

Clocks that don't have a divider are in our case all marked with the
CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
should modify the value pointed to by parent_rate, in order to propagate
the rate change to the parent, as explained in the documentation of
clk_set_rate().

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-5-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index a1a4f1a..dac6edc 100644 (file)
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -445,6 +445,8 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
                div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
        else if (clk_info->type & CGU_CLK_FIXDIV)
                div = clk_info->fixdiv.div;
+       else if (clk_hw_can_set_rate_parent(hw))
+               *parent_rate = req_rate;
 
        return DIV_ROUND_UP(*parent_rate, div);
 }