def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
-def FeaturePAN : SubtargetFeature<
- "pan", "HasPAN", "true",
- "Enables ARM v8.1 Privileged Access-Never extension">;
-
-def FeatureLOR : SubtargetFeature<
- "lor", "HasLOR", "true",
- "Enables ARM v8.1 Limited Ordering Regions extension">;
-
-def FeatureVH : SubtargetFeature<
- "vh", "HasVH", "true",
- "Enables ARM v8.1 Virtual Host extension">;
-
def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
"Enable ARMv8 PMUv3 Performance Monitors extension">;
def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
"Enable Statistical Profiling extension">;
-def FeaturePAN_RWV : SubtargetFeature<
- "pan-rwv", "HasPAN_RWV", "true",
- "Enable v8.2 PAN s1e1R and s1e1W Variants",
- [FeaturePAN]>;
-
-// UAO PState
-def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
- "Enable v8.2 UAO PState">;
-
-def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
- "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
-
def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
"Enable Scalable Vector Extension (SVE) instructions">;
"dotprod", "HasDotProd", "true",
"Enable dot product support">;
-def FeaturePA : SubtargetFeature<
- "pa", "HasPA", "true",
- "Enable v8.3-A Pointer Authentication enchancement">;
-
-def FeatureJS : SubtargetFeature<
- "jsconv", "HasJS", "true",
- "Enable v8.3-A JavaScript FP conversion enchancement",
- [FeatureFPARMv8]>;
-
-def FeatureCCIDX : SubtargetFeature<
- "ccidx", "HasCCIDX", "true",
- "Enable v8.3-A Extend of the CCSIDR number of sets">;
-
-def FeatureComplxNum : SubtargetFeature<
- "complxnum", "HasComplxNum", "true",
- "Enable v8.3-A Floating-point complex number support",
- [FeatureNEON]>;
-
-def FeatureNV : SubtargetFeature<
- "nv", "HasNV", "true",
- "Enable v8.4-A Nested Virtualization Enchancement">;
-
-def FeatureRASv8_4 : SubtargetFeature<
- "rasv8_4", "HasRASv8_4", "true",
- "Enable v8.4-A Reliability, Availability and Serviceability extension",
- [FeatureRAS]>;
-
-def FeatureMPAM : SubtargetFeature<
- "mpam", "HasMPAM", "true",
- "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
-
-def FeatureDIT : SubtargetFeature<
- "dit", "HasDIT", "true",
- "Enable v8.4-A Data Independent Timing instructions">;
-
-def FeatureTRACEV8_4 : SubtargetFeature<
- "tracev8.4", "HasTRACEV8_4", "true",
- "Enable v8.4-A Trace extension">;
-
-def FeatureAM : SubtargetFeature<
- "am", "HasAM", "true",
- "Enable v8.4-A Activity Monitors extension">;
-
-def FeatureSEL2 : SubtargetFeature<
- "sel2", "HasSEL2", "true",
- "Enable v8.4-A Secure Exception Level 2 extension">;
-
-def FeatureTLB_RMI : SubtargetFeature<
- "tlb-rmi", "HasTLB_RMI", "true",
- "Enable v8.4-A TLB Range and Maintenance Instructions">;
-
-def FeatureFMI : SubtargetFeature<
- "fmi", "HasFMI", "true",
- "Enable v8.4-A Flag Manipulation Instructions">;
-
-// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
-def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
- "Enable v8.4-A RCPC instructions with Immediate Offsets",
- [FeatureRCPC]>;
-
def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
"NegativeImmediates", "false",
"Convert immediates and instructions "
"Enable execution and data prediction invalidation instructions" >;
def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
- "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
+ "true", "Enable Cache Clean to Point of Deep Persistence" >;
def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
"true", "Enable Branch Target Identification" >;
//
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
- "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
- FeaturePAN, FeatureLOR, FeatureVH]>;
+ "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
- "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
- FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
+ "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
- "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,
- FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
+ "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>;
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
- "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
- FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
- FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
- FeatureFMI, FeatureRCPC_IMMO]>;
+ "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>;
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
let Inst{4-0} = Rd;
}
-//8.3 CompNum - Floating-point complex number support
multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype,
string asm, SDPatternOperator OpNode>{
- let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
+ let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {
def v4f16 : BaseSIMDThreeSameVectorComplex<0, U, 0b01, opcode, V64, rottype,
asm, ".4h",
[(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
(rottype i32:$rot)))]>;
}
- let Predicates = [HasComplxNum, HasNEON] in {
+ let Predicates = [HasV8_3a, HasNEON] in {
def v2f32 : BaseSIMDThreeSameVectorComplex<0, U, 0b10, opcode, V64, rottype,
asm, ".2s",
[(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode,
Operand rottype, string asm,
SDPatternOperator OpNode> {
- let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
+ let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {
def v4f16 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b01, opcode, V64,
rottype, asm, ".4h",
[(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
(rottype i32:$rot)))]>;
}
- let Predicates = [HasComplxNum, HasNEON] in {
+ let Predicates = [HasV8_3a, HasNEON] in {
def v2f32 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b10, opcode, V64,
rottype, asm, ".2s",
[(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
// classes.
multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,
string asm, SDPatternOperator OpNode> {
- let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
+ let Predicates = [HasV8_3a,HasNEON,HasFullFP16] in {
def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h",
".4h", ".h", []> {
let Inst{11} = idx{1};
let Inst{21} = idx{0};
}
- } // Predicates = HasComplxNum, HasNEON, HasFullFP16]
+ } // Predicates = [HasV8_3a,HasNEON,HasFullFP16]
- let Predicates = [HasComplxNum, HasNEON] in {
+ let Predicates = [HasV8_3a,HasNEON] in {
def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,
V128, V128, V128, VectorIndexD, rottype, asm, ".4s",
".4s", ".4s", ".s", []> {
let Inst{11} = idx{0};
let Inst{21} = 0;
}
- } // Predicates = [HasComplxNum, HasNEON]
+ } // Predicates = [HasV8_3a,HasNEON]
}
//----------------------------------------------------------------------------
AssemblerPredicate<"HasV8_4aOps", "armv8.4a">;
def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">,
AssemblerPredicate<"HasV8_5aOps", "armv8.5a">;
-def HasVH : Predicate<"Subtarget->hasVH()">,
- AssemblerPredicate<"FeatureVH", "vh">;
-
-def HasLOR : Predicate<"Subtarget->hasLOR()">,
- AssemblerPredicate<"FeatureLOR", "lor">;
-
-def HasPA : Predicate<"Subtarget->hasPA()">,
- AssemblerPredicate<"FeaturePA", "pa">;
-
-def HasJS : Predicate<"Subtarget->hasJS()">,
- AssemblerPredicate<"FeatureJS", "jsconv">;
-
-def HasCCIDX : Predicate<"Subtarget->hasCCIDX()">,
- AssemblerPredicate<"FeatureCCIDX", "ccidx">;
-
-def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">,
- AssemblerPredicate<"FeatureComplxNum", "complxnum">;
-
-def HasNV : Predicate<"Subtarget->hasNV()">,
- AssemblerPredicate<"FeatureNV", "nv">;
-
-def HasRASv8_4 : Predicate<"Subtarget->hasRASv8_4()">,
- AssemblerPredicate<"FeatureRASv8_4", "rasv8_4">;
-
-def HasMPAM : Predicate<"Subtarget->hasMPAM()">,
- AssemblerPredicate<"FeatureMPAM", "mpam">;
-
-def HasDIT : Predicate<"Subtarget->hasDIT()">,
- AssemblerPredicate<"FeatureDIT", "dit">;
-
-def HasTRACEV8_4 : Predicate<"Subtarget->hasTRACEV8_4()">,
- AssemblerPredicate<"FeatureTRACEV8_4", "tracev8.4">;
-
-def HasAM : Predicate<"Subtarget->hasAM()">,
- AssemblerPredicate<"FeatureAM", "am">;
-
-def HasSEL2 : Predicate<"Subtarget->hasSEL2()">,
- AssemblerPredicate<"FeatureSEL2", "sel2">;
-
-def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">,
- AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">;
-
-def HasFMI : Predicate<"Subtarget->hasFMI()">,
- AssemblerPredicate<"FeatureFMI", "fmi">;
-
-def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPCImm()">,
- AssemblerPredicate<"FeatureRCPC_IMMO", "rcpc-immo">;
-
def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
def HasNEON : Predicate<"Subtarget->hasNEON()">,
def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> {
let CRm = 0b0010;
let Inst{12} = 0;
- let Predicates = [HasTRACEV8_4];
+ let Predicates = [HasV8_4a];
}
}
}
// These pointer authentication isntructions require armv8.3a
-let Predicates = [HasPA] in {
+let Predicates = [HasV8_3a] in {
multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> {
def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>;
def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>;
defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>;
defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>;
-}
+ // v8.3a floating point conversion for javascript
+ let Predicates = [HasV8_3a, HasFPARMv8] in
+ def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
+ "fjcvtzs", []> {
+ let Inst{31} = 0;
+ }
-// v8.3a floating point conversion for javascript
-let Predicates = [HasJS, HasFPARMv8] in
-def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
- "fjcvtzs", []> {
- let Inst{31} = 0;
-} // HasJS, HasFPARMv8
+} // HasV8_3a
// v8.4 Flag manipulation instructions
-let Predicates = [HasFMI] in {
+let Predicates = [HasV8_4a] in {
def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
let Inst{20-5} = 0b0000001000000000;
}
def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">;
def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif",
"{\t$Rn, $imm, $mask}">;
-} // HasFMI
+} // HasV8_4a
// v8.5 flag manipulation instructions
let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in {
[(truncstorei8 GPR32z:$Rt,
(am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
-// Armv8.4 Weaker Release Consistency enhancements
-// LDAPR & STLR with Immediate Offset instructions
-let Predicates = [HasRCPC_IMMO] in {
+// Armv8.4 LDAPR & STLR with Immediate Offset instruction
+let Predicates = [HasV8_4a] in {
defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>;
defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>;
defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>;
def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
-let Predicates = [HasLOR] in {
+let Predicates = [HasV8_1a] in {
// v8.1a "Limited Order Region" extension load-acquire instructions
def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
bool HasFP16FML = false;
bool HasSPE = false;
- // ARMv8.1 extensions
- bool HasVH = false;
- bool HasPAN = false;
- bool HasLOR = false;
-
- // ARMv8.2 extensions
- bool HasPsUAO = false;
- bool HasPAN_RWV = false;
- bool HasCCPP = false;
-
- // ARMv8.3 extensions
- bool HasPA = false;
- bool HasJS = false;
- bool HasCCIDX = false;
- bool HasComplxNum = false;
-
- // ARMv8.4 extensions
- bool HasNV = false;
- bool HasRASv8_4 = false;
- bool HasMPAM = false;
- bool HasDIT = false;
- bool HasTRACEV8_4 = false;
- bool HasAM = false;
- bool HasSEL2 = false;
- bool HasTLB_RMI = false;
- bool HasFMI = false;
- bool HasRCPC_IMMO = false;
// ARMv8.4 Crypto extensions
bool HasSM4 = true;
bool HasSHA3 = true;
bool useAA() const override { return UseAA; }
- bool hasVH() const { return HasVH; }
- bool hasPAN() const { return HasPAN; }
- bool hasLOR() const { return HasLOR; }
-
- bool hasPsUAO() const { return HasPsUAO; }
- bool hasPAN_RWV() const { return HasPAN_RWV; }
- bool hasCCPP() const { return HasCCPP; }
-
- bool hasPA() const { return HasPA; }
- bool hasJS() const { return HasJS; }
- bool hasCCIDX() const { return HasCCIDX; }
- bool hasComplxNum() const { return HasComplxNum; }
-
- bool hasNV() const { return HasNV; }
- bool hasRASv8_4() const { return HasRASv8_4; }
- bool hasMPAM() const { return HasMPAM; }
- bool hasDIT() const { return HasDIT; }
- bool hasTRACEV8_4() const { return HasTRACEV8_4; }
- bool hasAM() const { return HasAM; }
- bool hasSEL2() const { return HasSEL2; }
- bool hasTLB_RMI() const { return HasTLB_RMI; }
- bool hasFMI() const { return HasFMI; }
- bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
-
bool useSmallAddressing() const {
switch (TLInfo.getTargetMachine().getCodeModel()) {
case CodeModel::Kernel:
include "llvm/TableGen/SearchableTable.td"
//===----------------------------------------------------------------------===//
-// Features that, for the compiler, only enable system operands and PStates
-//===----------------------------------------------------------------------===//
-
-def HasCCPP : Predicate<"Subtarget->hasCCPP()">,
- AssemblerPredicate<"FeatureCCPP", "ccpp">;
-
-def HasPAN : Predicate<"Subtarget->hasPAN()">,
- AssemblerPredicate<"FeaturePAN",
- "ARM v8.1 Privileged Access-Never extension">;
-
-def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">,
- AssemblerPredicate<"FeaturePsUAO",
- "ARM v8.2 UAO PState extension (psuao)">;
-
-def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">,
- AssemblerPredicate<"FeaturePAN_RWV",
- "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">;
-
-//===----------------------------------------------------------------------===//
// AT (address translate) instruction options.
//===----------------------------------------------------------------------===//
def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>;
def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>;
-let Requires = [{ {AArch64::FeaturePAN_RWV} }] in {
+let Requires = [{ {AArch64::HasV8_2aOps} }] in {
def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
}
def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>;
def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>;
-let Requires = [{ {AArch64::FeatureCCPP} }] in
+let Requires = [{ {AArch64::HasV8_2aOps} }] in
def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>;
let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in
bits<4> Encoding;
let Encoding = encoding;
- code Requires = [{ {AArch64::FeatureTRACEV8_4} }];
+ code Requires = [{ {AArch64::HasV8_4aOps} }];
}
def : TSB<"csync", 0>;
def : PState<"DAIFSet", 0b11110>;
def : PState<"DAIFClr", 0b11111>;
// v8.1a "Privileged Access Never" extension-specific PStates
-let Requires = [{ {AArch64::FeaturePAN} }] in
+let Requires = [{ {AArch64::HasV8_1aOps} }] in
def : PState<"PAN", 0b00100>;
-
// v8.2a "User Access Override" extension-specific PStates
-let Requires = [{ {AArch64::FeaturePsUAO} }] in
+let Requires = [{ {AArch64::HasV8_2aOps} }] in
def : PState<"UAO", 0b00011>;
// v8.4a timining insensitivity of data processing instructions
-let Requires = [{ {AArch64::FeatureDIT} }] in
+let Requires = [{ {AArch64::HasV8_4aOps} }] in
def : PState<"DIT", 0b11010>;
// v8.5a Spectre Mitigation
let Requires = [{ {AArch64::FeatureSSBS} }] in
def : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>;
def : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = [{ {AArch64::FeatureTLB_RMI} }] in {
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
+let Requires = [{ {AArch64::HasV8_4aOps} }] in {
// op1 CRn CRm op2
def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;
def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;
def : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>;
def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;
def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;
-} //FeatureTLB_RMI
+}
// Armv8.5-A Prediction Restriction by Context instruction options:
class PRCTX<string name, bits<4> crm> : SearchableTable {
def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
-
-//v8.3 CCIDX - extending the CCsIDr number of sets
def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
- let Requires = [{ {AArch64::FeatureCCIDX} }];
+ let Requires = [{ {AArch64::HasV8_3aOps} }];
}
def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;
def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;
def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;
def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>;
def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>;
-def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>;
+def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010> {
+ let Requires = [{ {AArch64::HasV8_2aOps} }];
+}
def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>;
def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>;
def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;
// v8.1a "Limited Ordering Regions" extension-specific system register
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureLOR} }] in
+let Requires = [{ {AArch64::HasV8_1aOps} }] in
def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;
// v8.2a "RAS extension" registers
def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>;
// v8.1a "Privileged Access Never" extension-specific system registers
-let Requires = [{ {AArch64::FeaturePAN} }] in
+let Requires = [{ {AArch64::HasV8_1aOps} }] in
def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>;
// v8.1a "Limited Ordering Regions" extension-specific system registers
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureLOR} }] in {
+let Requires = [{ {AArch64::HasV8_1aOps} }] in {
def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>;
def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>;
def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>;
def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>;
}
-// v8.1a "Virtualization Host extensions" system registers
+// v8.1a "Virtualization hos extensions" system registers
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureVH} }] in {
+let Requires = [{ {AArch64::HasV8_1aOps} }] in {
def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>;
def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>;
def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>;
}
// v8.2a registers
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeaturePsUAO} }] in
+let Requires = [{ {AArch64::HasV8_2aOps} }] in
def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>;
// v8.2a "Statistical Profiling extension" registers
// v8.3a "Pointer authentication extension" registers
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeaturePA} }] in {
+let Requires = [{ {AArch64::HasV8_3aOps} }] in {
def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>;
def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>;
def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>;
def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>;
}
-// v8.4 "Secure Exception Level 2 extension"
-let Requires = [{ {AArch64::FeatureSEL2} }] in {
+let Requires = [{ {AArch64::HasV8_4aOps} }] in {
+
// v8.4a "Virtualization secure second stage translation" registers
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>;
// v8.4a "Virtualization debug state" registers
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;
-} // FeatureSEL2
// v8.4a RAS registers
-// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureRASv8_4} }] in {
+// Op0 Op1 CRn CRm Op2
def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
def : RWSysReg<"ERXTS_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b111>;
def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>;
def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>;
def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;
-} // FeatureRASv8_4
// v8.4a MPAM registers
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureMPAM} }] in {
def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>;
def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>;
def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>;
def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>;
-} //FeatureMPAM
-// v8.4a Activitiy Monitor registers
+// v8.4a Activitiy monitor registers
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureAM} }] in {
def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>;
def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>;
def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>;
def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>;
def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>;
def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>;
-} //FeatureAM
// v8.4a Trace Extension registers
//
// but they are already defined above.
//
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in {
def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>;
def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>;
def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>;
-} //FeatureTRACEV8_4
// v8.4a Timining insensitivity of data processing instructions
-// DIT: Data Independent Timing instructions
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureDIT} }] in {
def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>;
-} //FeatureDIT
// v8.4a Enhanced Support for Nested Virtualization
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureNV} }] in {
def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>;
-} //FeatureNV
+
+} // HasV8_4aOps
// SVE control registers
// Op0 Op1 CRn CRm Op2
const char *Name;
const FeatureBitset Features;
} ExtensionMap[] = {
- {"crc", {AArch64::FeatureCRC}},
- {"sm4", {AArch64::FeatureSM4}},
- {"sha3", {AArch64::FeatureSHA3}},
- {"sha2", {AArch64::FeatureSHA2}},
- {"aes", {AArch64::FeatureAES}},
- {"crypto", {AArch64::FeatureCrypto}},
- {"fp", {AArch64::FeatureFPARMv8}},
- {"simd", {AArch64::FeatureNEON}},
- {"ras", {AArch64::FeatureRAS}},
- {"lse", {AArch64::FeatureLSE}},
- {"predctrl", {AArch64::FeaturePredCtrl}},
- {"ccdp", {AArch64::FeatureCacheDeepPersist}},
- {"mte", {AArch64::FeatureMTE}},
- {"tlb-rmi", {AArch64::FeatureTLB_RMI}},
- {"pan-rwv", {AArch64::FeaturePAN_RWV}},
- {"ccpp", {AArch64::FeatureCCPP}},
- // FIXME: Unsupported extensions
- {"pan", {}},
- {"lor", {}},
- {"rdma", {}},
- {"profile", {}},
+ { "crc", {AArch64::FeatureCRC} },
+ { "sm4", {AArch64::FeatureSM4} },
+ { "sha3", {AArch64::FeatureSHA3} },
+ { "sha2", {AArch64::FeatureSHA2} },
+ { "aes", {AArch64::FeatureAES} },
+ { "crypto", {AArch64::FeatureCrypto} },
+ { "fp", {AArch64::FeatureFPARMv8} },
+ { "simd", {AArch64::FeatureNEON} },
+ { "ras", {AArch64::FeatureRAS} },
+ { "lse", {AArch64::FeatureLSE} },
+ { "predctrl", {AArch64::FeaturePredCtrl} },
+ { "ccdp", {AArch64::FeatureCacheDeepPersist} },
+ { "mte", {AArch64::FeatureMTE} },
+
+ // FIXME: Unsupported extensions
+ { "pan", {} },
+ { "lor", {} },
+ { "rdma", {} },
+ { "profile", {} },
};
+
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
if (FBS[AArch64::HasV8_1aOps])
Str += "ARMv8.1a";
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a %s -o - | FileCheck %s
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a,+pan-rwv %s -o - | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-pan-rwv %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
at s1e1rp, x1
at s1e1wp, x2
// CHECK: at s1e1rp, x1 // encoding: [0x01,0x79,0x08,0xd5]
// CHECK: at s1e1wp, x2 // encoding: [0x22,0x79,0x08,0xd5]
-// ERROR: error: AT S1E1RP requires pan-rwv
-// ERROR: error: AT S1E1WP requires pan-rwv
+// ERROR: error: AT S1E1RP requires ARMv8.2a
+// ERROR: error: AT S1E1WP requires ARMv8.2a
--- /dev/null
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+ mrs x3, id_aa64mmfr2_el1
+// CHECK: mrs x3, ID_AA64MMFR2_EL1 // encoding: [0x43,0x07,0x38,0xd5]
+// ERROR: error: expected readable system register
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -o - %s | FileCheck %s
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ccpp -o - %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
dc cvap, x7
// CHECK: dc cvap, x7 // encoding: [0x27,0x7c,0x0b,0xd5]
-// ERROR: error: DC CVAP requires ccpp
+// ERROR: error: DC CVAP requires ARMv8.2a
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,-fullfp16 -o - %s 2>%t | \
-// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=NO-FP16
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,-fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=NO-FP16
// RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-NO-FP16 %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,+fullfp16 -o - %s 2>%t | \
-// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=FP16
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,+fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
// RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-FP16 %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-v8.3a,+fullfp16,+complxnum -o - %s 2>&1 | \
-// RUN: FileCheck %s --check-prefix=FP16
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-v8.3a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A
+
+
// ==== FCMLA vector ====
// Types
fcmla v0.4h, v1.4h, v2.4h, #0
// FP16: fcmla v0.4h, v1.4h, v2.4h, #0 // encoding: [0x20,0xc4,0x42,0x2e]
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.8h, v1.8h, v2.8h, #0
// FP16: fcmla v0.8h, v1.8h, v2.8h, #0 // encoding: [0x20,0xc4,0x42,0x6e]
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.2s, v1.2s, v2.2s, #0
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.4s, v1.4s, v2.4s, #0
// CHECK: fcmla v0.4s, v1.4s, v2.4s, #0 // encoding: [0x20,0xc4,0x82,0x6e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.2d, v1.2d, v2.2d, #0
// CHECK: fcmla v0.2d, v1.2d, v2.2d, #0 // encoding: [0x20,0xc4,0xc2,0x6e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
// Rotations
fcmla v0.2s, v1.2s, v2.2s, #0
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.2s, v1.2s, v2.2s, #90
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xcc,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.2s, v1.2s, v2.2s, #180
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #180 // encoding: [0x20,0xd4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.2s, v1.2s, v2.2s, #270
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xdc,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
// Invalid rotations
fcmla v0.2s, v1.2s, v2.2s, #1
fcadd v0.4h, v1.4h, v2.4h, #90
// FP16: fcadd v0.4h, v1.4h, v2.4h, #90 // encoding: [0x20,0xe4,0x42,0x2e]
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcadd v0.8h, v1.8h, v2.8h, #90
// FP16: fcadd v0.8h, v1.8h, v2.8h, #90 // encoding: [0x20,0xe4,0x42,0x6e]
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcadd v0.2s, v1.2s, v2.2s, #90
// CHECK: fcadd v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcadd v0.4s, v1.4s, v2.4s, #90
// CHECK: fcadd v0.4s, v1.4s, v2.4s, #90 // encoding: [0x20,0xe4,0x82,0x6e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcadd v0.2d, v1.2d, v2.2d, #90
// CHECK: fcadd v0.2d, v1.2d, v2.2d, #90 // encoding: [0x20,0xe4,0xc2,0x6e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
// Rotations
fcadd v0.2s, v1.2s, v2.2s, #90
// CHECK: fcadd v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcadd v0.2s, v1.2s, v2.2s, #270
// CHECK: fcadd v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xf4,0x82,0x2e]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
// Invalid rotations
fcadd v0.2s, v1.2s, v2.2s, #1
fcmla v0.4h, v1.4h, v2.h[0], #0
// FP16: fcmla v0.4h, v1.4h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x2f]
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.8h, v1.8h, v2.h[0], #0
// FP16: fcmla v0.8h, v1.8h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x6f]
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.2s, v1.2s, v2.s[0], #0
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction
fcmla v0.4s, v1.4s, v2.s[0], #0
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #0 // encoding: [0x20,0x10,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.2d, v1.2d, v2.d[0], #0
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction
// Rotations
fcmla v0.4s, v1.4s, v2.s[0], #90
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #90 // encoding: [0x20,0x30,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.4s, v1.4s, v2.s[0], #180
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #180 // encoding: [0x20,0x50,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.4s, v1.4s, v2.s[0], #270
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #270 // encoding: [0x20,0x70,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
// Valid indices
fcmla v0.4h, v1.4h, v2.h[1], #0
// FP16: fcmla v0.4h, v1.4h, v2.h[1], #0 // encoding: [0x20,0x10,0x62,0x2f]
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.8h, v1.8h, v2.h[3], #0
// FP16: fcmla v0.8h, v1.8h, v2.h[3], #0 // encoding: [0x20,0x18,0x62,0x6f]
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
fcmla v0.4s, v1.4s, v2.s[1], #0
// CHECK: fcmla v0.4s, v1.4s, v2.s[1], #0 // encoding: [0x20,0x18,0x82,0x6f]
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
// Invalid indices
fcmla v0.4h, v1.4h, v2.h[2], #0
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a -o - %s 2>&1 | \
-// RUN: FileCheck %s
-
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+jsconv -o - %s 2>&1 | \
-// RUN: FileCheck %s
-
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu %s 2>&1 | \
-// RUN: FileCheck --check-prefix=CHECK-JS %s
-
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+jsconv,-fp-armv8 -o - %s 2>&1 |\
-// RUN: FileCheck --check-prefix=CHECK-REQ %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-REQ < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fp-armv8 < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NOFP < %t %s
fjcvtzs w0, d0
// CHECK: fjcvtzs w0, d0 // encoding: [0x00,0x00,0x7e,0x1e]
-
-// CHECK-JS: error: instruction requires: jsconv
-
-// NOJS: error: instruction requires: jsconv
-
-// CHECK-REQ: error: instruction requires: fp-armv8 jsconv
+// CHECK-REQ: error: instruction requires: armv8.3a
+// CHECK-NOFP: error: instruction requires: fp-armv8
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a -o - %s 2>&1 | \
-// RUN: FileCheck --check-prefixes=CHECK,ALL %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2> %t | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu %s -o - > %t.1 2>%t.2
-// RUN: FileCheck --check-prefixes=ALL,NOENC %s < %t.1
-// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t.2
-
-// ALL: .text
mrs x0, apiakeylo_el1
mrs x0, apiakeyhi_el1
mrs x0, apibkeylo_el1
mrs x0, apdbkeyhi_el1
mrs x0, apgakeylo_el1
mrs x0, apgakeyhi_el1
-// ALL-EMPTY:
-// ALL-EMPTY:
-// CHECK-NEXT: mrs x0, APIAKeyLo_EL1 // encoding: [0x00,0x21,0x38,0xd5]
-// CHECK-NEXT: mrs x0, APIAKeyHi_EL1 // encoding: [0x20,0x21,0x38,0xd5]
-// CHECK-NEXT: mrs x0, APIBKeyLo_EL1 // encoding: [0x40,0x21,0x38,0xd5]
-// CHECK-NEXT: mrs x0, APIBKeyHi_EL1 // encoding: [0x60,0x21,0x38,0xd5]
-// CHECK-NEXT: mrs x0, APDAKeyLo_EL1 // encoding: [0x00,0x22,0x38,0xd5]
-// CHECK-NEXT: mrs x0, APDAKeyHi_EL1 // encoding: [0x20,0x22,0x38,0xd5]
-// CHECK-NEXT: mrs x0, APDBKeyLo_EL1 // encoding: [0x40,0x22,0x38,0xd5]
-// CHECK-NEXT: mrs x0, APDBKeyHi_EL1 // encoding: [0x60,0x22,0x38,0xd5]
-// CHECK-NEXT: mrs x0, APGAKeyLo_EL1 // encoding: [0x00,0x23,0x38,0xd5]
-// CHECK-NEXT: mrs x0, APGAKeyHi_EL1 // encoding: [0x20,0x23,0x38,0xd5]
+
+// CHECK: mrs x0, APIAKeyLo_EL1 // encoding: [0x00,0x21,0x38,0xd5]
+// CHECK: mrs x0, APIAKeyHi_EL1 // encoding: [0x20,0x21,0x38,0xd5]
+// CHECK: mrs x0, APIBKeyLo_EL1 // encoding: [0x40,0x21,0x38,0xd5]
+// CHECK: mrs x0, APIBKeyHi_EL1 // encoding: [0x60,0x21,0x38,0xd5]
+// CHECK: mrs x0, APDAKeyLo_EL1 // encoding: [0x00,0x22,0x38,0xd5]
+// CHECK: mrs x0, APDAKeyHi_EL1 // encoding: [0x20,0x22,0x38,0xd5]
+// CHECK: mrs x0, APDBKeyLo_EL1 // encoding: [0x40,0x22,0x38,0xd5]
+// CHECK: mrs x0, APDBKeyHi_EL1 // encoding: [0x60,0x22,0x38,0xd5]
+// CHECK: mrs x0, APGAKeyLo_EL1 // encoding: [0x00,0x23,0x38,0xd5]
+// CHECK: mrs x0, APGAKeyHi_EL1 // encoding: [0x20,0x23,0x38,0xd5]
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apiakeylo_el1
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apiakeyhi_el1
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apibkeylo_el1
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apibkeyhi_el1
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apdakeylo_el1
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apdakeyhi_el1
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apdbkeylo_el1
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apdbkeyhi_el1
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apgakeylo_el1
// CHECK-REQ: error: expected readable system register
-// CHECK-REQ-NEXT: mrs x0, apgakeyhi_el1
msr apiakeylo_el1, x0
msr apiakeyhi_el1, x0
msr apdbkeyhi_el1, x0
msr apgakeylo_el1, x0
msr apgakeyhi_el1, x0
-// ALL-EMPTY:
-// ALL-EMPTY:
-// CHECK-NEXT: msr APIAKeyLo_EL1, x0 // encoding: [0x00,0x21,0x18,0xd5]
-// CHECK-NEXT: msr APIAKeyHi_EL1, x0 // encoding: [0x20,0x21,0x18,0xd5]
-// CHECK-NEXT: msr APIBKeyLo_EL1, x0 // encoding: [0x40,0x21,0x18,0xd5]
-// CHECK-NEXT: msr APIBKeyHi_EL1, x0 // encoding: [0x60,0x21,0x18,0xd5]
-// CHECK-NEXT: msr APDAKeyLo_EL1, x0 // encoding: [0x00,0x22,0x18,0xd5]
-// CHECK-NEXT: msr APDAKeyHi_EL1, x0 // encoding: [0x20,0x22,0x18,0xd5]
-// CHECK-NEXT: msr APDBKeyLo_EL1, x0 // encoding: [0x40,0x22,0x18,0xd5]
-// CHECK-NEXT: msr APDBKeyHi_EL1, x0 // encoding: [0x60,0x22,0x18,0xd5]
-// CHECK-NEXT: msr APGAKeyLo_EL1, x0 // encoding: [0x00,0x23,0x18,0xd5]
-// CHECK-NEXT: msr APGAKeyHi_EL1, x0 // encoding: [0x20,0x23,0x18,0xd5]
+
+// CHECK: msr APIAKeyLo_EL1, x0 // encoding: [0x00,0x21,0x18,0xd5]
+// CHECK: msr APIAKeyHi_EL1, x0 // encoding: [0x20,0x21,0x18,0xd5]
+// CHECK: msr APIBKeyLo_EL1, x0 // encoding: [0x40,0x21,0x18,0xd5]
+// CHECK: msr APIBKeyHi_EL1, x0 // encoding: [0x60,0x21,0x18,0xd5]
+// CHECK: msr APDAKeyLo_EL1, x0 // encoding: [0x00,0x22,0x18,0xd5]
+// CHECK: msr APDAKeyHi_EL1, x0 // encoding: [0x20,0x22,0x18,0xd5]
+// CHECK: msr APDBKeyLo_EL1, x0 // encoding: [0x40,0x22,0x18,0xd5]
+// CHECK: msr APDBKeyHi_EL1, x0 // encoding: [0x60,0x22,0x18,0xd5]
+// CHECK: msr APGAKeyLo_EL1, x0 // encoding: [0x00,0x23,0x18,0xd5]
+// CHECK: msr APGAKeyHi_EL1, x0 // encoding: [0x20,0x23,0x18,0xd5]
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apiakeylo_el1, x0
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apiakeyhi_el1, x0
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apibkeylo_el1, x0
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apibkeyhi_el1, x0
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apdakeylo_el1, x0
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apdakeyhi_el1, x0
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apdbkeylo_el1, x0
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apdbkeyhi_el1, x0
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apgakeylo_el1, x0
// CHECK-REQ: error: expected writable system register or pstate
-// CHECK-REQ-NEXT: msr apgakeyhi_el1, x0
-// ALL-EMPTY:
-// ALL-EMPTY:
paciasp
-// CHECK-NEXT: paciasp // encoding: [0x3f,0x23,0x03,0xd5]
-// NOENC-NEXT: paciasp
+// CHECK: paciasp // encoding: [0x3f,0x23,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
autiasp
-// CHECK-NEXT: autiasp // encoding: [0xbf,0x23,0x03,0xd5]
-// NOENC-NEXT: autiasp
+// CHECK: autiasp // encoding: [0xbf,0x23,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
paciaz
-// CHECK-NEXT: paciaz // encoding: [0x1f,0x23,0x03,0xd5]
-// NOENC-NEXT: paciaz
+// CHECK: paciaz // encoding: [0x1f,0x23,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
autiaz
-// CHECK-NEXT: autiaz // encoding: [0x9f,0x23,0x03,0xd5]
-// NOENC-NEXT: autiaz
+// CHECK: autiaz // encoding: [0x9f,0x23,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
pacia1716
-// CHECK-NEXT: pacia1716 // encoding: [0x1f,0x21,0x03,0xd5]
-// NOENC-NEXT: pacia1716
+// CHECK: pacia1716 // encoding: [0x1f,0x21,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
autia1716
-// CHECK-NEXT: autia1716 // encoding: [0x9f,0x21,0x03,0xd5]
-// NOENC-NEXT: autia1716
+// CHECK: autia1716 // encoding: [0x9f,0x21,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
pacibsp
-// CHECK-NEXT: pacibsp // encoding: [0x7f,0x23,0x03,0xd5]
-// NOENC-NEXT: pacibsp
+// CHECK: pacibsp // encoding: [0x7f,0x23,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
autibsp
-// CHECK-NEXT: autibsp // encoding: [0xff,0x23,0x03,0xd5]
-// NOENC-NEXT: autibsp
+// CHECK: autibsp // encoding: [0xff,0x23,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
pacibz
-// CHECK-NEXT: pacibz // encoding: [0x5f,0x23,0x03,0xd5]
-// NOENC-NEXT: pacibz
+// CHECK: pacibz // encoding: [0x5f,0x23,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
autibz
-// CHECK-NEXT: autibz // encoding: [0xdf,0x23,0x03,0xd5]
-// NOENC-NEXT: autibz
+// CHECK: autibz // encoding: [0xdf,0x23,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
pacib1716
-// CHECK-NEXT: pacib1716 // encoding: [0x5f,0x21,0x03,0xd5]
-// NOENC-NEXT: pacib1716
+// CHECK: pacib1716 // encoding: [0x5f,0x21,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
autib1716
-// CHECK-NEXT: autib1716 // encoding: [0xdf,0x21,0x03,0xd5]
-// NOENC-NEXT: autib1716
+// CHECK: autib1716 // encoding: [0xdf,0x21,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
xpaclri
-// CHECK-NEXT: xpaclri // encoding: [0xff,0x20,0x03,0xd5]
-// NOENC-NEXT: xpaclri
+// CHECK: xpaclri // encoding: [0xff,0x20,0x03,0xd5]
+// CHECK-REQ-NOT: error: instruction requires: armv8.3a
-// ALL-EMPTY:
pacia x0, x1
-// CHECK-NEXT: pacia x0, x1 // encoding: [0x20,0x00,0xc1,0xda]
-// CHECK-REQ-NEXT: ^
-// CHECK-REQ-NEXT: error: instruction requires: pa
-// CHECK-REQ-NEXT: pacia x0, x1
+// CHECK: pacia x0, x1 // encoding: [0x20,0x00,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
autia x0, x1
-// CHECK-NEXT: autia x0, x1 // encoding: [0x20,0x10,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: autia x0, x1
+// CHECK: autia x0, x1 // encoding: [0x20,0x10,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
pacda x0, x1
-// CHECK-NEXT: pacda x0, x1 // encoding: [0x20,0x08,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: pacda x0, x1
+// CHECK: pacda x0, x1 // encoding: [0x20,0x08,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
autda x0, x1
-// CHECK-NEXT: autda x0, x1 // encoding: [0x20,0x18,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: autda x0, x1
+// CHECK: autda x0, x1 // encoding: [0x20,0x18,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
pacib x0, x1
-// CHECK-NEXT: pacib x0, x1 // encoding: [0x20,0x04,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: pacib x0, x1
+// CHECK: pacib x0, x1 // encoding: [0x20,0x04,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
autib x0, x1
-// CHECK-NEXT: autib x0, x1 // encoding: [0x20,0x14,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: autib x0, x1
+// CHECK: autib x0, x1 // encoding: [0x20,0x14,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
pacdb x0, x1
-// CHECK-NEXT: pacdb x0, x1 // encoding: [0x20,0x0c,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: pacdb x0, x1
+// CHECK: pacdb x0, x1 // encoding: [0x20,0x0c,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
autdb x0, x1
-// CHECK-NEXT: autdb x0, x1 // encoding: [0x20,0x1c,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: autdb x0, x1
+// CHECK: autdb x0, x1 // encoding: [0x20,0x1c,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
pacga x0, x1, x2
-// CHECK-NEXT: pacga x0, x1, x2 // encoding: [0x20,0x30,0xc2,0x9a]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: pacga x0, x1, x2
+// CHECK: pacga x0, x1, x2 // encoding: [0x20,0x30,0xc2,0x9a]
+// CHECK-REQ: error: instruction requires: armv8.3a
paciza x0
-// CHECK-NEXT: paciza x0 // encoding: [0xe0,0x23,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: paciza x0
+// CHECK: paciza x0 // encoding: [0xe0,0x23,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
autiza x0
-// CHECK-NEXT: autiza x0 // encoding: [0xe0,0x33,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: autiza x0
+// CHECK: autiza x0 // encoding: [0xe0,0x33,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
pacdza x0
-// CHECK-NEXT: pacdza x0 // encoding: [0xe0,0x2b,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: pacdza x0
+// CHECK: pacdza x0 // encoding: [0xe0,0x2b,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
autdza x0
-// CHECK-NEXT: autdza x0 // encoding: [0xe0,0x3b,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: autdza x0
+// CHECK: autdza x0 // encoding: [0xe0,0x3b,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
pacizb x0
-// CHECK-NEXT: pacizb x0 // encoding: [0xe0,0x27,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: pacizb x0
+// CHECK: pacizb x0 // encoding: [0xe0,0x27,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
autizb x0
-// CHECK-NEXT: autizb x0 // encoding: [0xe0,0x37,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: autizb x0
+// CHECK: autizb x0 // encoding: [0xe0,0x37,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
pacdzb x0
-// CHECK-NEXT: pacdzb x0 // encoding: [0xe0,0x2f,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: pacdzb x0
+// CHECK: pacdzb x0 // encoding: [0xe0,0x2f,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
autdzb x0
-// CHECK-NEXT: autdzb x0 // encoding: [0xe0,0x3f,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: autdzb x0
+// CHECK: autdzb x0 // encoding: [0xe0,0x3f,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
xpaci x0
-// CHECK-NEXT: xpaci x0 // encoding: [0xe0,0x43,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: xpaci x0
+// CHECK: xpaci x0 // encoding: [0xe0,0x43,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
xpacd x0
-// CHECK-NEXT: xpacd x0 // encoding: [0xe0,0x47,0xc1,0xda]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: xpacd x0
+// CHECK: xpacd x0 // encoding: [0xe0,0x47,0xc1,0xda]
+// CHECK-REQ: error: instruction requires: armv8.3a
braa x0, x1
-// CHECK-EMPTY:
-// CHECK-NEXT: braa x0, x1 // encoding: [0x01,0x08,0x1f,0xd7]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: braa x0, x1
+// CHECK: braa x0, x1 // encoding: [0x01,0x08,0x1f,0xd7]
+// CHECK-REQ: error: instruction requires: armv8.3a
brab x0, x1
-// CHECK-NEXT: brab x0, x1 // encoding: [0x01,0x0c,0x1f,0xd7]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: brab x0, x1
+// CHECK: brab x0, x1 // encoding: [0x01,0x0c,0x1f,0xd7]
+// CHECK-REQ: error: instruction requires: armv8.3a
blraa x0, x1
-// CHECK-NEXT: blraa x0, x1 // encoding: [0x01,0x08,0x3f,0xd7]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: blraa x0, x1
+// CHECK: blraa x0, x1 // encoding: [0x01,0x08,0x3f,0xd7]
+// CHECK-REQ: error: instruction requires: armv8.3a
blrab x0, x1
-// CHECK-NEXT: blrab x0, x1 // encoding: [0x01,0x0c,0x3f,0xd7]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: blrab x0, x1
+// CHECK: blrab x0, x1 // encoding: [0x01,0x0c,0x3f,0xd7]
+// CHECK-REQ: error: instruction requires: armv8.3a
braaz x0
-// CHECK-EMPTY:
-// CHECK-NEXT: braaz x0 // encoding: [0x1f,0x08,0x1f,0xd6]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: braaz x0
+// CHECK: braaz x0 // encoding: [0x1f,0x08,0x1f,0xd6]
+// CHECK-REQ: error: instruction requires: armv8.3a
brabz x0
-// CHECK-NEXT: brabz x0 // encoding: [0x1f,0x0c,0x1f,0xd6]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: brabz x0
+// CHECK: brabz x0 // encoding: [0x1f,0x0c,0x1f,0xd6]
+// CHECK-REQ: error: instruction requires: armv8.3a
blraaz x0
-// CHECK-NEXT: blraaz x0 // encoding: [0x1f,0x08,0x3f,0xd6]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: blraaz x0
+// CHECK: blraaz x0 // encoding: [0x1f,0x08,0x3f,0xd6]
+// CHECK-REQ: error: instruction requires: armv8.3a
blrabz x0
-// CHECK-NEXT: blrabz x0 // encoding: [0x1f,0x0c,0x3f,0xd6]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: blrabz x0
+// CHECK: blrabz x0 // encoding: [0x1f,0x0c,0x3f,0xd6]
+// CHECK-REQ: error: instruction requires: armv8.3a
retaa
-// CHECK-NEXT: retaa // encoding: [0xff,0x0b,0x5f,0xd6]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: retaa
+// CHECK: retaa // encoding: [0xff,0x0b,0x5f,0xd6]
+// CHECK-REQ: error: instruction requires: armv8.3a
retab
-// CHECK-NEXT: retab // encoding: [0xff,0x0f,0x5f,0xd6]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: retab
+// CHECK: retab // encoding: [0xff,0x0f,0x5f,0xd6]
+// CHECK-REQ: error: instruction requires: armv8.3a
eretaa
-// CHECK-NEXT: eretaa // encoding: [0xff,0x0b,0x9f,0xd6]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: eretaa
+// CHECK: eretaa // encoding: [0xff,0x0b,0x9f,0xd6]
+// CHECK-REQ: error: instruction requires: armv8.3a
eretab
-// CHECK-NEXT: eretab // encoding: [0xff,0x0f,0x9f,0xd6]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: eretab
+// CHECK: eretab // encoding: [0xff,0x0f,0x9f,0xd6]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldraa x0, [x1, 4088]
-// CHECK-NEXT: ldraa x0, [x1, #4088] // encoding: [0x20,0xf4,0x3f,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldraa x0, [x1, 4088]
+// CHECK: ldraa x0, [x1, #4088] // encoding: [0x20,0xf4,0x3f,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldraa x0, [x1, -4096]
-// CHECK-NEXT: ldraa x0, [x1, #-4096] // encoding: [0x20,0x04,0x60,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldraa x0, [x1, -4096]
+// CHECK: ldraa x0, [x1, #-4096] // encoding: [0x20,0x04,0x60,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldrab x0, [x1, 4088]
-// CHECK-NEXT: ldrab x0, [x1, #4088] // encoding: [0x20,0xf4,0xbf,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldrab x0, [x1, 4088]
+// CHECK: ldrab x0, [x1, #4088] // encoding: [0x20,0xf4,0xbf,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldrab x0, [x1, -4096]
-// CHECK-NEXT: ldrab x0, [x1, #-4096] // encoding: [0x20,0x04,0xe0,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldrab x0, [x1, -4096]
+// CHECK: ldrab x0, [x1, #-4096] // encoding: [0x20,0x04,0xe0,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldraa x0, [x1, 4088]!
-// CHECK-NEXT: ldraa x0, [x1, #4088]! // encoding: [0x20,0xfc,0x3f,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldraa x0, [x1, 4088]!
+// CHECK: ldraa x0, [x1, #4088]! // encoding: [0x20,0xfc,0x3f,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldraa x0, [x1, -4096]!
-// CHECK-NEXT: ldraa x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x60,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldraa x0, [x1, -4096]!
+// CHECK: ldraa x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x60,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldrab x0, [x1, 4088]!
-// CHECK-NEXT: ldrab x0, [x1, #4088]! // encoding: [0x20,0xfc,0xbf,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldrab x0, [x1, 4088]!
+// CHECK: ldrab x0, [x1, #4088]! // encoding: [0x20,0xfc,0xbf,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldrab x0, [x1, -4096]!
-// CHECK-NEXT: ldrab x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xe0,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldrab x0, [x1, -4096]!
+// CHECK: ldrab x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xe0,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldraa x0, [x1]
-// CHECK-NEXT: ldraa x0, [x1] // encoding: [0x20,0x04,0x20,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldraa x0, [x1]
+// CHECK: ldraa x0, [x1] // encoding: [0x20,0x04,0x20,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
ldrab x0, [x1]
-// CHECK-NEXT: ldrab x0, [x1] // encoding: [0x20,0x04,0xa0,0xf8]
-// CHECK-REQ: error: instruction requires: pa
-// CHECK-REQ-NEXT: ldrab x0, [x1]
+// CHECK: ldrab x0, [x1] // encoding: [0x20,0x04,0xa0,0xf8]
+// CHECK-REQ: error: instruction requires: armv8.3a
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a %s -o - | \
-// RUN: FileCheck %s
-
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fmi %s -o - 2>&1 | \
-// RUN: FileCheck %s
-
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a %s -o - 2>&1 | \
-// RUN: FileCheck %s --check-prefix=ERROR
-
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-fmi %s -o - 2>&1 | \
-// RUN: FileCheck %s --check-prefix=ERROR
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s --check-prefix=CHECK
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
//------------------------------------------------------------------------------
// Armv8.4-A flag manipulation instructions
//CHECK-NEXT: rmif x1, #63, #15 // encoding: [0x2f,0x84,0x1f,0xba]
//CHECK-NEXT: rmif xzr, #63, #15 // encoding: [0xef,0x87,0x1f,0xba]
-//ERROR: error: instruction requires: fmi
-//ERROR-NEXT: cfinv
-//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
-//ERROR-NEXT: setf8 w1
-//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
-//ERROR-NEXT: setf8 wzr
-//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
-//ERROR-NEXT: setf16 w1
-//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
-//ERROR-NEXT: setf16 wzr
-//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
-//ERROR-NEXT: rmif x1, #63, #15
-//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
-//ERROR-NEXT: rmif xzr, #63, #15
-//ERROR-NEXT: ^
+//CHECK-ERROR: error: instruction requires: armv8.4a
+//CHECK-ERROR-NEXT: cfinv
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
+//CHECK-ERROR-NEXT: setf8 w1
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
+//CHECK-ERROR-NEXT: setf8 wzr
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
+//CHECK-ERROR-NEXT: setf16 w1
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
+//CHECK-ERROR-NEXT: setf16 wzr
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
+//CHECK-ERROR-NEXT: rmif x1, #63, #15
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a
+//CHECK-ERROR-NEXT: rmif xzr, #63, #15
+//CHECK-ERROR-NEXT: ^
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a -o - %s | FileCheck %s
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a,+rcpc-immo -o - %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-rcpc-immo -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s --check-prefix=CHECK
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
//------------------------------------------------------------------------------
// Armv8.4-A LDAPR and STLR instructions with immediate offsets
//CHECK-NEXT: ldapur x13, [x4, #255] // encoding: [0x8d,0xf0,0x4f,0xd9]
//CHECK-NEXT: ldapur x14, [sp, #9] // encoding: [0xee,0x93,0x40,0xd9]
-//CHECK-NO-V84: error: instruction requires: rcpc-immo
+//CHECK-NO-V84: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLURB WZR, [X10]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLURB W1, [X10]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLURB W1, [X10, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: stlurb w2, [x11, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLURB W3, [SP, #-3]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapurb wzr, [x12]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapurb w4, [x12]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapurb w4, [x12, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURB W5, [X13, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURB W6, [SP, #-2]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSB W7, [X14]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSB W7, [X14, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapursb w8, [x15, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapursb w9, [sp, #-1]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSB X0, [X16]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSB X0, [X16, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSB X1, [X17, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapursb x2, [sp, #0]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapursb x2, [sp]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: stlurh w10, [x18]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: stlurh w10, [x18, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLURH W11, [X19, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLURH W12, [SP, #1]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURH W13, [X20]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURH W13, [X20, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapurh w14, [x21, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURH W15, [SP, #2]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSH W16, [X22]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSH W16, [X22, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSH W17, [X23, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapursh w18, [sp, #3]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapursh x3, [x24]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapursh x3, [x24, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSH X4, [X25, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSH X5, [SP, #4]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLUR W19, [X26]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLUR W19, [X26, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: stlur w20, [x27, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLUR W21, [SP, #5]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPUR W22, [X28]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPUR W22, [X28, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPUR W23, [X29, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapur w24, [sp, #6]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapursw x6, [x30]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapursw x6, [x30, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSW X7, [X0, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPURSW X8, [SP, #7]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLUR X9, [X1]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLUR X9, [X1, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: stlur x10, [x2, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: STLUR X11, [SP, #8]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPUR X12, [X3]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPUR X12, [X3, #-256]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: LDAPUR X13, [X4, #255]
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo
+//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a
//CHECK-NO-V84-NEXT: ldapur x14, [sp, #9]
//CHECK-NO-V84-NEXT: ^
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK
// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+tlb-rmi < %s 2> %t | FileCheck %s --check-prefix=CHECK
-// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-tlb-rmi < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
// Outer shareable TLB maintenance instructions:
tlbi vmalle1os
//CHECK-ERROR-NEXT: tlbi vae1os, sp
//CHECK-ERROR-NEXT: ^
-//CHECK-NO-V84: error: TLBI VMALLE1OS requires tlb-rmi
+//CHECK-NO-V84: error: TLBI VMALLE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vmalle1os
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vae1os, xzr
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vae1os, x0
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI ASIDE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI ASIDE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi aside1os, x1
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VAAE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VAAE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vaae1os, x2
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VALE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VALE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vale1os, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VAALE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VAALE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vaale1os, x4
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI IPAS2E1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI IPAS2E1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi ipas2e1os, x5
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI IPAS2LE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI IPAS2LE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi ipas2le1os, x6
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VAE2OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VAE2OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vae2os, x7
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VALE2OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VALE2OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vale2os, x8
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VMALLS12E1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VMALLS12E1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vmalls12e1os
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VAE3OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VAE3OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vae3os, x9
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI VALE3OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI VALE3OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi vale3os, x10
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI ALLE2OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI ALLE2OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi alle2os
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI ALLE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI ALLE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi alle1os
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI ALLE3OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI ALLE3OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi alle3os
//CHECK-NO-V84-NEXT: ^
//CHECK-ERROR-NEXT: tlbi rvae1, sp
//CHECK-ERROR-NEXT: ^
-//CHECK-NO-V84: error: TLBI RVAE1 requires tlb-rmi
+//CHECK-NO-V84: error: TLBI RVAE1 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvae1, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAAE1 requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAAE1 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvaae1, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE1 requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE1 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale1, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAALE1 requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAALE1 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvaale1, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE1IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAE1IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvae1is, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAAE1IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAAE1IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvaae1is, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE1IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE1IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale1is, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAALE1IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAALE1IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvaale1is, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvae1os, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAAE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAAE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvaae1os, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale1os, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAALE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAALE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvaale1os, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi ripas2e1is, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi ripas2le1is, x3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1 requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi ripas2e1, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1 requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi ripas2le1, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi ripas2e1os, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi ripas2le1os, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE2 requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAE2 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvae2, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE2 requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE2 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale2, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE2IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAE2IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvae2is, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE2IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE2IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale2is, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE2OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAE2OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvae2os, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE2OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE2OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale2os, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE3 requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAE3 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvae3, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3 requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3 requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale3, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE3IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAE3IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvae3is, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3IS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3IS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale3is, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVAE3OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVAE3OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvae3os, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale3os, X3
//CHECK-NO-V84-NEXT: ^
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires tlb-rmi
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires ARMv8.4a
//CHECK-NO-V84-NEXT: tlbi rvale3os, XZR
//CHECK-NO-V84-NEXT: ^
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a -o - 2>&1 %s | \
-// RUN: FileCheck %s
-
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+tracev8.4 -o - 2>&1 %s | \
-// RUN: FileCheck %s
-
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a -o - %s 2>&1 | \
-// RUN: FileCheck %s --check-prefix=CHECK-ERROR
-
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-tracev8.4 -o - %s 2>&1 | \
-// RUN: FileCheck %s --check-prefixes NOFEATURE,CHECK-ERROR
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s --check-prefix=CHECK
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
//------------------------------------------------------------------------------
// ARMV8.4-A Debug, Trace and PMU Extensions
//CHECK-ERROR: mrs x0, TRFCR_EL12
//CHECK-ERROR: ^
-//CHECK-ERROR: error: instruction requires: tracev8.4
+//CHECK-ERROR: error: instruction requires: armv8.4a