{
if (IsReadyToRunCompilation())
{
- SIZE_T value = 0;
+ TARGET_POINTER_TYPE value = 0;
pZapWriter->Write(&value, sizeof(value));
return;
}
- SIZE_T token = CORCOMPILE_TAG_TOKEN(GetBlob()->GetRVA());
+ TARGET_POINTER_TYPE token = CORCOMPILE_TAG_TOKEN(GetBlob()->GetRVA());
pZapWriter->Write(&token, sizeof(token));
}
{
ZapImage * pImage = ZapImage::GetImage(pZapWriter);
- PVOID cell;
+ TARGET_POINTER_TYPE cell;
pImage->WriteReloc(&cell, 0, m_pDelayLoadHelper, 0, IMAGE_REL_BASED_PTR);
pZapWriter->Write(&cell, sizeof(cell));
}
{
ZapImage * pImage = ZapImage::GetImage(pZapWriter);
- PVOID cell;
+ TARGET_POINTER_TYPE cell;
pImage->WriteReloc(&cell, 0, m_pDelayLoadHelper, 0, IMAGE_REL_BASED_PTR);
pZapWriter->Write(&cell, sizeof(cell));
}
{
ZapImage * pImage = ZapImage::GetImage(pZapWriter);
- PVOID cell;
+ TARGET_POINTER_TYPE cell;
pImage->WriteReloc(&cell, 0, m_pDelayLoadHelper, 0, IMAGE_REL_BASED_PTR);
pZapWriter->Write(&cell, sizeof(cell));
}
break;
case IMAGE_REL_BASED_PTR:
- *(UNALIGNED TADDR *)location = (TADDR)targetOffset;
+ *(UNALIGNED TARGET_POINTER_TYPE *)location = (TARGET_POINTER_TYPE)targetOffset;
break;
#if defined(_TARGET_X86_) || defined(_TARGET_AMD64_)
// Misaligned relocs disable ASLR on ARM. We should never ever emit them.
_ASSERTE(IS_ALIGNED(rva, TARGET_POINTER_SIZE));
#endif
- *(UNALIGNED TADDR *)pLocation = pActualTarget;
+ *(UNALIGNED TARGET_POINTER_TYPE *)pLocation = (TARGET_POINTER_TYPE)pActualTarget;
break;
case IMAGE_REL_BASED_RELPTR:
// description of IMAGE_REL_BASED_REL_THUMB_MOV32_PCREL
const UINT32 offsetCorrection = 12;
- UINT32 imm32 = pActualTarget - (pSite + offsetCorrection);
+ UINT32 imm32 = UINT32(pActualTarget - (pSite + offsetCorrection));
PutThumb2Mov32((UINT16 *)pLocation, imm32);
}
// IMAGE_REL_BASED_THUMB_BRANCH24 does not need base reloc entry
return;
-#endif
+#endif // defined(_TARGET_ARM_)
#if defined(_TARGET_ARM64_)
case IMAGE_REL_ARM64_BRANCH26:
{