Entries in v850_opcodes reordered to put same named entries adjacent to each other.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d12f127aa7aed1b6369ef47f2006480fffd4c619..496b0f6b3dcf7dc8cd87935bb58d342f3ec69c5d 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+Tue Sep 16 09:48:50 1997  Nick Clifton  <nickc@cygnus.com>
+
+       * v850-opc.c (v850_opcodes): Fields reordered to allow assembler
+       parser to work.
+
 Tue Sep 16 10:01:00 1997  Gavin Koch  <gavin@cygnus.com>
 
        * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret.

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 36f224333ba06e638618ecbb4536ff665d0202b7..a0c2f9c4d1373bd2793344affaf506f5ebb9562a 100644 (file)
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -548,16 +548,24 @@ const struct v850_opcode v850_opcodes[] =
 /* load/store instructions */
 /* start-sanitize-v850eq */
 { "sld.bu",    one (0x0300),           one (0x0780),           {D7,   EP,   R2_NOTR0}, 1, PROCESSOR_V850EQ },
-{ "sld.hu",    one (0x0400),           one (0x0780),           {D8_7, EP,   R2_NOTR0}, 1, PROCESSOR_V850EQ },
-{ "sld.b",      one (0x0060),          one (0x07f0),           {D4,   EP,   R2},       1, PROCESSOR_V850EQ },
-{ "sld.h",      one (0x0070),          one (0x07f0),           {D5_4, EP,   R2},       1, PROCESSOR_V850EQ },
 /* end-sanitize-v850eq */
-{ "sld.b",     one (0x0300),           one (0x0780),           {D7,   EP,   R2},       1, PROCESSOR_ALL },
-{ "sld.h",     one (0x0400),           one (0x0780),           {D8_7, EP,   R2},       1, PROCESSOR_ALL },
 /* start-sanitize-v850e */
 { "sld.bu",     one (0x0060),          one (0x07f0),           {D4,   EP,   R2_NOTR0}, 1, PROCESSOR_V850E },
+/* end-sanitize-v850e */
+/* start-sanitize-v850eq */
+{ "sld.hu",    one (0x0400),           one (0x0780),           {D8_7, EP,   R2_NOTR0}, 1, PROCESSOR_V850EQ },
+/* end-sanitize-v850eq */
+/* start-sanitize-v850e */
 { "sld.hu",     one (0x0070),          one (0x07f0),           {D5_4, EP,   R2_NOTR0}, 1, PROCESSOR_V850E },
 /* end-sanitize-v850e */
+/* start-sanitize-v850eq */
+{ "sld.b",      one (0x0060),          one (0x07f0),           {D4,   EP,   R2},       1, PROCESSOR_V850EQ },
+/* end-sanitize-v850eq */
+{ "sld.b",     one (0x0300),           one (0x0780),           {D7,   EP,   R2},       1, PROCESSOR_ALL },
+/* start-sanitize-v850eq */
+{ "sld.h",      one (0x0070),          one (0x07f0),           {D5_4, EP,   R2},       1, PROCESSOR_V850EQ },
+/* end-sanitize-v850eq */
+{ "sld.h",     one (0x0400),           one (0x0780),           {D8_7, EP,   R2},       1, PROCESSOR_ALL },
 { "sld.w",     one (0x0500),           one (0x0781),           {D8_6, EP,   R2},       1, PROCESSOR_ALL },
 { "sst.b",     one (0x0380),           one (0x0780),           {R2,   D7,   EP},       2, PROCESSOR_ALL },
 { "sst.h",     one (0x0480),           one (0x0780),           {R2,   D8_7, EP},       2, PROCESSOR_ALL },