[Aarch64] Support an ARMv8.2 system register.

ARMv8.2 adds a new system register id_aa64mmfr2_el1. This patch adds
support for the register to binutils, making it available when
-march=armv8.2-a is selected.

opcodes/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
	(aarch64_sys_reg_supported_p): Add ARMv8.2 system register
	feature test.

gas/testsuite/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: New.
	* gas/aarch64/sysreg-2.s: New.

Change-Id: I767f18a60e2bd70ce74c89f6abfe07afdc9e601f

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index aae4691..faf5282 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/sysreg-2.d: New.
+       * gas/aarch64/sysreg-2.s: New.
+
 2015-11-24  Christophe Monat <christophe.monat@st.com>
 
        * gas/arm/thumb2_ldr_immediate_armv6t2.s: Added high register

diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d
new file mode 100644 (file)
index 0000000..f0fe533
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-2.d
@@ -0,0 +1,11 @@
+#objdump: -dr
+#as: -march=armv8.2-a
+
+.*:     file .*
+
+
+Disassembly of section .text:
+
+0000000000000000 <.*>:
+   [0-9a-f]+:  d5380725        mrs     x5, id_aa64mmfr1_el1
+   [0-9a-f]+:  d5380747        mrs     x7, id_aa64mmfr2_el1

diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s
new file mode 100644 (file)
index 0000000..f519682
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-2.s
@@ -0,0 +1,15 @@
+/* sysreg-2.s Test file for ARMv8.2 system registers.  */
+
+       .macro rw_sys_reg sys_reg xreg r w
+       .ifc \w, 1
+       msr \sys_reg, \xreg
+       .endif
+       .ifc \r, 1
+       mrs \xreg, \sys_reg
+       .endif
+       .endm
+
+       .text
+
+       rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x5 r=1 w=0
+       rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 08f0c1b..d773eec 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
+       (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
+       feature test.
+
 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 
        * arm-dis.c (print_insn): Also set is_thumb for Mach-O.

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a19f36f..9323217 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2801,6 +2801,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1),    0 }, /* RO */
   { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0),    0 }, /* RO */
   { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1),    0 }, /* RO */
+  { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT }, /* RO */
   { "id_aa64afr0_el1",  CPENC(3,0,C0,C5,4),    0 }, /* RO */
   { "id_aa64afr1_el1",  CPENC(3,0,C0,C5,5),    0 }, /* RO */
   { "clidr_el1",        CPENC(3,1,C0,C0,1),    0 }, /* RO */
@@ -3135,6 +3136,10 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
        || reg->value == CPENC (3, 5, C14, C3, 1)
        || reg->value == CPENC (3, 5, C14, C3, 2))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+
+  /* ARMv8.2 features.  */
+  if (reg->value == CPENC (3, 0, C0, C7, 2)
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
 
   return TRUE;