intel/devinfo: dedicated entries for XeHP

Also fixing the max URB entries for VS stage.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>

diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c
index 9b4eada..12ee193 100644 (file)
--- a/src/intel/dev/intel_device_info.c
+++ b/src/intel/dev/intel_device_info.c
@@ -1048,15 +1048,44 @@ static const struct intel_device_info intel_device_info_sg1 = {
    GFX12_DG1_SG1_FEATURES,
 };
 
+#define XEHP_URB_MIN_MAX_ENTRIES                        \
+   .min_entries = {                                     \
+      [MESA_SHADER_VERTEX]    = 64,                     \
+      [MESA_SHADER_TESS_EVAL] = 34,                     \
+   },                                                   \
+   .max_entries = {                                     \
+      [MESA_SHADER_VERTEX]    = 3832, /* BSpec 47138 */ \
+      [MESA_SHADER_TESS_CTRL] = 1548, /* BSpec 47137 */ \
+      [MESA_SHADER_TESS_EVAL] = 3576, /* BSpec 47135 */ \
+      [MESA_SHADER_GEOMETRY]  = 1548, /* BSpec 47136 */ \
+   }
+
 #define XEHP_FEATURES(_gt, _slices, _l3)                        \
-   GFX12_FEATURES(_gt, _slices, _l3),                           \
+   GFX8_FEATURES,                                               \
+   .has_64bit_float = false,                                    \
+   .has_64bit_int = false,                                      \
+   .has_integer_dword_mul = false,                              \
+   .gt = _gt, .num_slices = _slices, .l3_banks = _l3,           \
+   .ver = 12,                                                   \
+   .has_pln = false,                                            \
+   .has_sample_with_hiz = false,                                \
+   .max_vs_threads = 546,  /* BSpec 46312 */                    \
+   .max_gs_threads = 336,  /* BSpec 46299 */                    \
+   .max_tcs_threads = 336, /* BSpec 46300 */                    \
+   .max_tes_threads = 546, /* BSpec 46298 */                    \
+   .max_threads_per_psd = 64,                                   \
+   .max_cs_threads = 112, /* threads per DSS */                 \
+   .urb = {                                                     \
+      .size = 768, /* For intel_stub_gpu */                     \
+      XEHP_URB_MIN_MAX_ENTRIES,                                 \
+   },                                                           \
    .num_thread_per_eu = 8 /* BSpec 44472 */,                    \
+   .max_eus_per_subslice = 16,                                  \
    .verx10 = 125,                                               \
    .has_llc = false,                                            \
    .has_lsc = true,                                             \
    .has_local_mem = true,                                       \
    .has_aux_map = false,                                        \
-   .urb.size = 768, /* For intel_stub_gpu */                    \
    .simulator_id = 29
 
 #define DG2_FEATURES                                            \