// Quotient_S_One = Quotient - 1
auto Quotient_S_One = B.buildSub(S32, Quotient, One);
- // Div = (Tmp1 ? Quotient : Quotient_A_One)
- auto Div = B.buildSelect(S32, Tmp1, Quotient, Quotient_A_One);
+ // Div = (Tmp1 ? Quotient_A_One : Quotient)
+ auto Div = B.buildSelect(S32, Tmp1, Quotient_A_One, Quotient);
// Div = (Remainder_GE_Zero ? Div : Quotient_S_One)
if (IsRem) {
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX6: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX6: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C3]]
; GFX6: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C3]]
- ; GFX6: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[UMULH5]], [[ADD7]]
+ ; GFX6: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[ADD7]], [[UMULH5]]
; GFX6: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB8]]
; GFX6: [[XOR6:%[0-9]+]]:_(s32) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX6: [[XOR7:%[0-9]+]]:_(s32) = G_XOR [[SELECT7]], [[XOR6]]
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX8: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX8: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C3]]
; GFX8: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C3]]
- ; GFX8: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[UMULH5]], [[ADD7]]
+ ; GFX8: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[ADD7]], [[UMULH5]]
; GFX8: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB8]]
; GFX8: [[XOR6:%[0-9]+]]:_(s32) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX8: [[XOR7:%[0-9]+]]:_(s32) = G_XOR [[SELECT7]], [[XOR6]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX9: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX9: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C3]]
; GFX9: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C3]]
- ; GFX9: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[UMULH5]], [[ADD7]]
+ ; GFX9: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[ADD7]], [[UMULH5]]
; GFX9: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB8]]
; GFX9: [[XOR6:%[0-9]+]]:_(s32) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX9: [[XOR7:%[0-9]+]]:_(s32) = G_XOR [[SELECT7]], [[XOR6]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C4]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C4]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX6: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX6: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C4]]
; GFX6: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C4]]
- ; GFX6: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[UMULH5]], [[ADD7]]
+ ; GFX6: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[ADD7]], [[UMULH5]]
; GFX6: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB8]]
; GFX6: [[XOR6:%[0-9]+]]:_(s32) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX6: [[XOR7:%[0-9]+]]:_(s32) = G_XOR [[SELECT7]], [[XOR6]]
; GFX8: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C4]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C4]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX8: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX8: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C4]]
; GFX8: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C4]]
- ; GFX8: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[UMULH5]], [[ADD7]]
+ ; GFX8: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[ADD7]], [[UMULH5]]
; GFX8: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB8]]
; GFX8: [[XOR6:%[0-9]+]]:_(s32) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX8: [[XOR7:%[0-9]+]]:_(s32) = G_XOR [[SELECT7]], [[XOR6]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C4]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C4]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX9: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX9: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C4]]
; GFX9: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C4]]
- ; GFX9: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[UMULH5]], [[ADD7]]
+ ; GFX9: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[ADD7]], [[UMULH5]]
; GFX9: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB8]]
; GFX9: [[XOR6:%[0-9]+]]:_(s32) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX9: [[XOR7:%[0-9]+]]:_(s32) = G_XOR [[SELECT7]], [[XOR6]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD3]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD3]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[XOR2]]
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C2]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C2]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD1]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: $vgpr0 = COPY [[SELECT3]](s32)
; GFX8-LABEL: name: test_udiv_s32
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C2]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C2]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD1]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: $vgpr0 = COPY [[SELECT3]](s32)
; GFX9-LABEL: name: test_udiv_s32
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C2]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C2]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD1]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: $vgpr0 = COPY [[SELECT3]](s32)
%0:_(s32) = COPY $vgpr0
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C2]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C2]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD1]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV3]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C2]]
; GFX6: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C2]]
- ; GFX6: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[UMULH5]], [[ADD3]]
+ ; GFX6: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[ADD3]], [[UMULH5]]
; GFX6: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB7]]
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT3]](s32), [[SELECT7]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C2]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C2]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD1]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV3]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX8: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C2]]
; GFX8: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C2]]
- ; GFX8: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[UMULH5]], [[ADD3]]
+ ; GFX8: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[ADD3]], [[UMULH5]]
; GFX8: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB7]]
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT3]](s32), [[SELECT7]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C2]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C2]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[ADD1]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV3]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C2]]
; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C2]]
- ; GFX9: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[UMULH5]], [[ADD3]]
+ ; GFX9: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[ADD3]], [[UMULH5]]
; GFX9: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB7]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT3]](s32), [[SELECT7]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C4]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C4]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX6: [[AND5:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C4]]
; GFX6: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C4]]
- ; GFX6: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND5]](s1), [[UMULH5]], [[ADD3]]
+ ; GFX6: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND5]](s1), [[ADD3]], [[UMULH5]]
; GFX6: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB7]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX8: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C4]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C4]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX8: [[AND5:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C4]]
; GFX8: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C4]]
- ; GFX8: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND5]](s1), [[UMULH5]], [[ADD3]]
+ ; GFX8: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND5]](s1), [[ADD3]], [[UMULH5]]
; GFX8: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB7]]
; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX8: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C4]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C4]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX9: [[AND5:%[0-9]+]]:_(s1) = G_AND [[ICMP4]], [[ICMP5]]
; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH5]], [[C4]]
; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[UMULH5]], [[C4]]
- ; GFX9: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND5]](s1), [[UMULH5]], [[ADD3]]
+ ; GFX9: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND5]](s1), [[ADD3]], [[UMULH5]]
; GFX9: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT6]], [[SUB7]]
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT7]](s32)
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX8: $vgpr0 = COPY [[COPY4]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32)
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX8: $vgpr0 = COPY [[COPY4]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UMULH2]], [[C3]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMULH2]], [[C3]]
- ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[UMULH2]], [[ADD1]]
+ ; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s1), [[ADD1]], [[UMULH2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SELECT2]], [[SUB3]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32)
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1
; GISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v3, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; GISEL-NEXT: v_xor_b32_e32 v1, v2, v2
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, s3, v1
; GISEL-NEXT: v_cmp_le_u32_e64 s[0:1], s4, v4
; GISEL-NEXT: s_and_b64 s[0:1], s[0:1], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; GISEL-NEXT: s_xor_b32 s0, s2, s2
; GISEL-NEXT: v_xor_b32_e32 v0, s0, v0
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v14, v2
; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v3
; GISEL-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v9, v4, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v4, v9, s[6:7]
; GISEL-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v12, v5, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v12, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v1, v13, v1, s[4:5]
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v6
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v2
; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v5, v3, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v1
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
; CHECK-NEXT: v_cmp_ge_u32_e64 s[6:7], v14, v2
; CHECK-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v3
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v9, v4, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v4, v9, s[6:7]
; CHECK-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; CHECK-NEXT: v_cndmask_b32_e64 v1, v12, v5, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v1, v5, v12, s[6:7]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v1, v13, v1, s[4:5]
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v6
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v2
; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v5, v3, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v1
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
; CHECK-NEXT: v_cmp_ge_u32_e64 s[6:7], v14, v2
; CHECK-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v3
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v9, v4, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v4, v9, s[6:7]
; CHECK-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; CHECK-NEXT: v_cndmask_b32_e64 v1, v12, v5, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v1, v5, v12, s[6:7]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v1, v13, v1, s[4:5]
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v6
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1
; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v5, v3, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v1, v2, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v14, v2
; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v3
; GISEL-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v9, v4, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v4, v9, s[6:7]
; GISEL-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v12, v5, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v12, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v1, v13, v1, s[4:5]
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v6
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1
; GISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v3, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; GISEL-NEXT: v_xor_b32_e32 v1, v2, v2
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v14, v2
; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v3
; GISEL-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v9, v4, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v4, v9, s[6:7]
; GISEL-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v12, v5, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v12, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v1, v13, v1, s[4:5]
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v6
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
; GISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v4, v2, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, s0, v1
; GISEL-NEXT: v_cmp_le_u32_e64 s[0:1], s1, v4
; GISEL-NEXT: s_and_b64 s[0:1], s[0:1], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-NEXT: ; return to shader part epilog
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v12, v2
; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v3
; GISEL-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v7, v4, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v4, v7, s[6:7]
; GISEL-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v10, v5, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v10, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v1, v11, v1, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v4, v2, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = udiv i32 %num, 4096
; CHECK-NEXT: v_cmp_ge_u32_e64 s[6:7], v11, v2
; CHECK-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v2
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v6, v3, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v3, v6, s[6:7]
; CHECK-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; CHECK-NEXT: v_cndmask_b32_e64 v1, v9, v4, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v1, v4, v9, s[6:7]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[4:5]
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v5
; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v3, v1, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = udiv i32 %num, 1235195
; CHECK-NEXT: v_cmp_le_u32_e64 s[6:7], s8, v11
; CHECK-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v2
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v6, v3, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v3, v6, s[6:7]
; CHECK-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; CHECK-NEXT: v_cndmask_b32_e64 v1, v9, v4, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v1, v4, v9, s[6:7]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[4:5]
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v4, v2, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl i32 4096, %y
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v12, v2
; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v3
; GISEL-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v7, v4, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v4, v7, s[6:7]
; GISEL-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v10, v5, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v10, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v1, v11, v1, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31]
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
; GISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v4, v2, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v12, v2
; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v0, v3
; GISEL-NEXT: s_and_b64 s[6:7], s[6:7], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v7, v4, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v4, v7, s[6:7]
; GISEL-NEXT: s_and_b64 s[6:7], s[8:9], s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v10, v5, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v10, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v1, v11, v1, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v4, v1, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v1, v4, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v4, v5, v0, vcc
; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: BB0_4:
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, s0, v1
; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v4
; CHECK-NEXT: s_and_b64 s[0:1], s[0:1], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; CHECK-NEXT: BB1_4:
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v8, v1
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v4
; CGP-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CGP-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5]
+; CGP-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB2_4:
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v6
; CGP-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CGP-NEXT: v_cndmask_b32_e64 v2, v5, v3, s[4:5]
+; CGP-NEXT: v_cndmask_b32_e64 v2, v3, v5, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v4, v7, v2, vcc
; CGP-NEXT: v_mov_b32_e32 v5, 0
; CGP-NEXT: BB2_8:
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v4
; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v3, v1, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v2, v5, v0, vcc
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: BB7_4:
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v10
; CGP-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CGP-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[4:5]
+; CGP-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB8_4:
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v8
; CGP-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; CGP-NEXT: v_cndmask_b32_e64 v2, v5, v3, s[4:5]
+; CGP-NEXT: v_cndmask_b32_e64 v2, v3, v5, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v4, v6, v2, vcc
; CGP-NEXT: v_mov_b32_e32 v5, 0
; CGP-NEXT: BB8_8:
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
; GISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v0, v4, v2, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: s_setpc_b64 s[30:31]