CHIPSET(0x9BE6, cfl_gt2, "CML GT2", "Intel(R) UHD Graphics P630")
CHIPSET(0x9BF6, cfl_gt2, "CML GT2", "Intel(R) UHD Graphics P630")
-CHIPSET(0x5A49, cnl_gt0_5, "CNL GT0.5", "Intel(R) HD Graphics")
-CHIPSET(0x5A4A, cnl_gt0_5, "CNL GT0.5", "Intel(R) HD Graphics")
-CHIPSET(0x5A41, cnl_gt1, "CNL GT1", "Intel(R) HD Graphics")
-CHIPSET(0x5A42, cnl_gt1, "CNL GT1", "Intel(R) HD Graphics")
-CHIPSET(0x5A44, cnl_gt1, "CNL GT1", "Intel(R) HD Graphics")
-CHIPSET(0x5A59, cnl_gt1_5, "CNL GT1.5", "Intel(R) HD Graphics")
-CHIPSET(0x5A5A, cnl_gt1_5, "CNL GT1.5", "Intel(R) HD Graphics")
-CHIPSET(0x5A5C, cnl_gt1_5, "CNL GT1.5", "Intel(R) HD Graphics")
-CHIPSET(0x5A50, cnl_gt2, "CNL GT2", "Intel(R) HD Graphics")
-CHIPSET(0x5A51, cnl_gt2, "CNL GT2", "Intel(R) HD Graphics")
-CHIPSET(0x5A52, cnl_gt2, "CNL GT2", "Intel(R) HD Graphics")
-CHIPSET(0x5A54, cnl_gt2, "CNL GT2", "Intel(R) HD Graphics")
-
CHIPSET(0x8A50, icl_gt2, "ICL GT2", "Intel(R) HD Graphics")
CHIPSET(0x8A51, icl_gt2, "ICL GT2", "Intel(R) Iris(R) Plus Graphics")
CHIPSET(0x8A52, icl_gt2, "ICL GT2", "Intel(R) Iris(R) Plus Graphics")
{ "cfl", 0x3E9B },
{ "whl", 0x3EA1 },
{ "cml", 0x9b41 },
- { "cnl", 0x5a52 },
{ "icl", 0x8a52 },
{ "ehl", 0x4500 },
{ "jsl", 0x4E71 },
.simulator_id = 24,
};
-#define GEN10_HW_INFO \
- .gen = 10, \
- .num_thread_per_eu = 7, \
- .max_vs_threads = 728, \
- .max_gs_threads = 432, \
- .max_tcs_threads = 432, \
- .max_tes_threads = 624, \
- .max_cs_threads = 56, \
- .timestamp_frequency = 19200000, \
- .urb = { \
- .min_entries = { \
- [MESA_SHADER_VERTEX] = 64, \
- [MESA_SHADER_TESS_EVAL] = 34, \
- }, \
- .max_entries = { \
- [MESA_SHADER_VERTEX] = 3936, \
- [MESA_SHADER_TESS_CTRL] = 896, \
- [MESA_SHADER_TESS_EVAL] = 2064, \
- [MESA_SHADER_GEOMETRY] = 832, \
- }, \
- }
-
#define subslices(args...) { args, }
-#define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
- GEN8_FEATURES, \
- GEN10_HW_INFO, \
- .has_sample_with_hiz = true, \
- .gt = _gt, \
- .num_slices = _slices, \
- .num_subslices = _subslices, \
- .num_eu_per_subslice = 8, \
- .l3_banks = _l3
-
-static const struct gen_device_info gen_device_info_cnl_gt0_5 = {
- /* GT0.5 */
- GEN10_FEATURES(1, 1, subslices(2), 2),
- .is_cannonlake = true,
- .simulator_id = 15,
-};
-
-static const struct gen_device_info gen_device_info_cnl_gt1 = {
- /* GT1 */
- GEN10_FEATURES(1, 1, subslices(3), 3),
- .is_cannonlake = true,
- .simulator_id = 15,
-};
-
-static const struct gen_device_info gen_device_info_cnl_gt1_5 = {
- /* GT 1.5 */
- GEN10_FEATURES(1, 2, subslices(2, 2), 6),
- .is_cannonlake = true,
- .simulator_id = 15,
-};
-
-static const struct gen_device_info gen_device_info_cnl_gt2 = {
- /* GT2 */
- GEN10_FEATURES(2, 2, subslices(3, 2), 6),
- .is_cannonlake = true,
- .simulator_id = 15,
-};
-
#define GEN11_HW_INFO \
.gen = 11, \
.has_pln = false, \