[(set_attr "type" "clz")
(set_attr "mode" "<MODE>")])
+
+(define_insn "*clo<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (clz:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))))]
+ "ISA_HAS_CLZ_CLO"
+ "<d>clo\t%0,%1"
+ [(set_attr "type" "clz")
+ (set_attr "mode" "<MODE>")])
+
;;
;; ...................
;;
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "(HAS_CLZ)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 unsigned int foo(unsigned int x)
+{
+ return __builtin_clz (~x);
+}
+
+/* { dg-final { scan-assembler-not "\tclz\t" } } */
+/* { dg-final { scan-assembler "\tclo\t" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "(HAS_CLZ)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 unsigned int foo(unsigned int x)
+{
+ return __builtin_clz (x);
+}
+
+/* { dg-final { scan-assembler "\tclz\t" } } */
warnings "-w"
dump "-fdump-.*"
ins "HAS_INS"
+ clz "HAS_CLZ"
dmul "NOT_HAS_DMUL"
ldc "HAS_LDC"
movn "HAS_MOVN"
#
# - paired-single instructions(*)
# - odd numbered single precision registers
+ # - clz clo instructions
#
# (*) Note that we don't support MIPS V at the moment.
} elseif { $isa_rev < 1
&& ([mips_have_test_option_p options "-mpaired-single"]
|| ([mips_have_test_option_p options "-modd-spreg"]
+ || [mips_have_test_option_p options "HAS_CLZ"]
&& ![mips_have_test_option_p options "-mfp64"]))} {
if { $gp_size == 32 } {
mips_make_test_option options "-mips32"