phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write

inno_write is used to configure 0xaa reg, that also hold the
POST_PLL_POWER_DOWN bit.
When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not
taken into consideration.

Fix this by keeping the power down bit until configuration is complete.
Also reorder the reg write order for consistency.

Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230615171005.2251032-5-jonas@kwiboo.se
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index f027e0a..fe7fa9a 100644 (file)
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
 
        inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
        if (cfg->postdiv == 1) {
-               inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS);
                inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
                           RK3328_POST_PLL_PRE_DIV(cfg->prediv));
+               inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS |
+                          RK3328_POST_PLL_POWER_DOWN);
        } else {
                v = (cfg->postdiv / 2) - 1;
                v &= RK3328_POST_PLL_POST_DIV_MASK;
@@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
                inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
                           RK3328_POST_PLL_PRE_DIV(cfg->prediv));
                inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
-                          RK3328_POST_PLL_REFCLK_SEL_TMDS);
+                          RK3328_POST_PLL_REFCLK_SEL_TMDS |
+                          RK3328_POST_PLL_POWER_DOWN);
        }
 
        for (v = 0; v < 14; v++)