namespace llvm {
-class FunctionPass;
class ARCTargetMachine;
+class FunctionPass;
+class PassRegistry;
FunctionPass *createARCISelDag(ARCTargetMachine &TM,
CodeGenOpt::Level OptLevel);
FunctionPass *createARCExpandPseudosPass();
FunctionPass *createARCOptAddrMode();
FunctionPass *createARCBranchFinalizePass();
+void initializeARCDAGToDAGISelPass(PassRegistry &);
} // end namespace llvm
using namespace llvm;
+#define DEBUG_TYPE "arc-isel"
+#define PASS_NAME "ARC DAG->DAG Pattern Instruction Selection"
+
/// ARCDAGToDAGISel - ARC specific code to select ARC machine
/// instructions for SelectionDAG operations.
namespace {
public:
static char ID;
+ ARCDAGToDAGISel() = delete;
+
ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {}
bool SelectAddrModeImm(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectAddrModeFar(SDValue Addr, SDValue &Base, SDValue &Offset);
- StringRef getPassName() const override {
- return "ARC DAG->DAG Pattern Instruction Selection";
- }
-
// Include the pieces autogenerated from the target description.
#include "ARCGenDAGISel.inc"
};
char ARCDAGToDAGISel::ID;
+INITIALIZE_PASS(ARCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
} // end anonymous namespace
/// This pass converts a legalized DAG into a ARC-specific DAG, ready for
// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {
RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget());
+ PassRegistry &PR = *PassRegistry::getPassRegistry();
+ initializeARCDAGToDAGISelPass(PR);
}
TargetTransformInfo
class Function;
class FunctionPass;
class InstructionSelector;
-class MachineInstr;
class MCInst;
+class MachineInstr;
class PassRegistry;
Pass *createMVETailPredicationPass();
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
ARMAsmPrinter &AP);
-void initializeARMParallelDSPPass(PassRegistry &);
-void initializeARMLoadStoreOptPass(PassRegistry &);
-void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
+void initializeARMBlockPlacementPass(PassRegistry &);
void initializeARMBranchTargetsPass(PassRegistry &);
void initializeARMConstantIslandsPass(PassRegistry &);
+void initializeARMDAGToDAGISelPass(PassRegistry &);
void initializeARMExpandPseudoPass(PassRegistry &);
-void initializeThumb2SizeReducePass(PassRegistry &);
-void initializeThumb2ITBlockPass(PassRegistry &);
-void initializeMVEVPTBlockPass(PassRegistry &);
-void initializeMVETPAndVPTOptimisationsPass(PassRegistry &);
+void initializeARMFixCortexA57AES1742098Pass(PassRegistry &);
+void initializeARMLoadStoreOptPass(PassRegistry &);
void initializeARMLowOverheadLoopsPass(PassRegistry &);
-void initializeARMBlockPlacementPass(PassRegistry &);
-void initializeMVETailPredicationPass(PassRegistry &);
-void initializeMVEGatherScatterLoweringPass(PassRegistry &);
+void initializeARMParallelDSPPass(PassRegistry &);
+void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
void initializeARMSLSHardeningPass(PassRegistry &);
+void initializeMVEGatherScatterLoweringPass(PassRegistry &);
void initializeMVELaneInterleavingPass(PassRegistry &);
-void initializeARMFixCortexA57AES1742098Pass(PassRegistry &);
+void initializeMVETPAndVPTOptimisationsPass(PassRegistry &);
+void initializeMVETailPredicationPass(PassRegistry &);
+void initializeMVEVPTBlockPass(PassRegistry &);
+void initializeThumb2ITBlockPass(PassRegistry &);
+void initializeThumb2SizeReducePass(PassRegistry &);
} // end namespace llvm
using namespace llvm;
#define DEBUG_TYPE "arm-isel"
+#define PASS_NAME "ARM Instruction Selection"
static cl::opt<bool>
DisableShifterOp("disable-shifter-op", cl::Hidden,
public:
static char ID;
+ ARMDAGToDAGISel() = delete;
+
explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, tm, OptLevel) {}
return true;
}
- StringRef getPassName() const override { return "ARM Instruction Selection"; }
-
void PreprocessISelDAG() override;
/// getI32Imm - Return a target constant of type i32 with the specified
char ARMDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(ARMDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
/// operand. If so Imm will receive the 32-bit value.
static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
initializeARMSLSHardeningPass(Registry);
initializeMVELaneInterleavingPass(Registry);
initializeARMFixCortexA57AES1742098Pass(Registry);
+ initializeARMDAGToDAGISelPass(Registry);
}
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
class AVRTargetMachine;
class FunctionPass;
+class PassRegistry;
Pass *createAVRShiftExpandPass();
FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
FunctionPass *createAVRFrameAnalyzerPass();
FunctionPass *createAVRBranchSelectionPass();
-void initializeAVRShiftExpandPass(PassRegistry &);
+void initializeAVRDAGToDAGISelPass(PassRegistry &);
void initializeAVRExpandPseudoPass(PassRegistry &);
+void initializeAVRShiftExpandPass(PassRegistry &);
/// Contains the AVR backend.
namespace AVR {
#include "llvm/Support/raw_ostream.h"
#define DEBUG_TYPE "avr-isel"
+#define PASS_NAME "AVR DAG->DAG Instruction Selection"
-namespace llvm {
+using namespace llvm;
+
+namespace {
/// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form).
class AVRDAGToDAGISel : public SelectionDAGISel {
public:
static char ID;
+ AVRDAGToDAGISel() = delete;
+
AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
- StringRef getPassName() const override {
- return "AVR DAG->DAG Instruction Selection";
- }
-
bool runOnMachineFunction(MachineFunction &MF) override;
bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
const AVRSubtarget *Subtarget;
};
+} // namespace
+
char AVRDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(AVRDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<AVRSubtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
}
}
-FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+FunctionPass *llvm::createAVRISelDag(AVRTargetMachine &TM,
+ CodeGenOpt::Level OptLevel) {
return new AVRDAGToDAGISel(TM, OptLevel);
}
-
-} // end of namespace llvm
-
auto &PR = *PassRegistry::getPassRegistry();
initializeAVRExpandPseudoPass(PR);
initializeAVRShiftExpandPass(PR);
+ initializeAVRDAGToDAGISelPass(PR);
}
const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
#include "MCTargetDesc/BPFMCTargetDesc.h"
#include "llvm/IR/PassManager.h"
#include "llvm/Pass.h"
-#include "llvm/PassRegistry.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class BPFTargetMachine;
+class PassRegistry;
ModulePass *createBPFAdjustOpt();
ModulePass *createBPFCheckAndAdjustIR();
FunctionPass *createBPFMIPreEmitPeepholePass();
FunctionPass *createBPFMIPreEmitCheckingPass();
+void initializeBPFAbstractMemberAccessLegacyPassPass(PassRegistry &);
void initializeBPFAdjustOptPass(PassRegistry&);
void initializeBPFCheckAndAdjustIRPass(PassRegistry&);
-
-void initializeBPFAbstractMemberAccessLegacyPassPass(PassRegistry &);
-void initializeBPFPreserveDITypePass(PassRegistry&);
-void initializeBPFIRPeepholePass(PassRegistry&);
-void initializeBPFMISimplifyPatchablePass(PassRegistry&);
+void initializeBPFDAGToDAGISelPass(PassRegistry &);
+void initializeBPFIRPeepholePass(PassRegistry &);
void initializeBPFMIPeepholePass(PassRegistry&);
-void initializeBPFMIPeepholeTruncElimPass(PassRegistry&);
-void initializeBPFMIPreEmitPeepholePass(PassRegistry&);
+void initializeBPFMIPeepholeTruncElimPass(PassRegistry &);
void initializeBPFMIPreEmitCheckingPass(PassRegistry&);
+void initializeBPFMIPreEmitPeepholePass(PassRegistry &);
+void initializeBPFMISimplifyPatchablePass(PassRegistry &);
+void initializeBPFPreserveDITypePass(PassRegistry &);
class BPFAbstractMemberAccessPass
: public PassInfoMixin<BPFAbstractMemberAccessPass> {
using namespace llvm;
#define DEBUG_TYPE "bpf-isel"
+#define PASS_NAME "BPF DAG->DAG Pattern Instruction Selection"
// Instruction Selector Implementation
namespace {
public:
static char ID;
+ BPFDAGToDAGISel() = delete;
+
explicit BPFDAGToDAGISel(BPFTargetMachine &TM)
: SelectionDAGISel(ID, TM), Subtarget(nullptr) {}
- StringRef getPassName() const override {
- return "BPF DAG->DAG Pattern Instruction Selection";
- }
-
bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through.
Subtarget = &MF.getSubtarget<BPFSubtarget>();
char BPFDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(BPFDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
// ComplexPattern used on BPF Load/Store instructions
bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
// if Address is FI, get the TargetFrameIndex.
initializeBPFCheckAndAdjustIRPass(PR);
initializeBPFMIPeepholePass(PR);
initializeBPFMIPeepholeTruncElimPass(PR);
+ initializeBPFDAGToDAGISelPass(PR);
}
// DataLayout: little or big endian
FunctionPass *createCSKYConstantIslandPass();
void initializeCSKYConstantIslandsPass(PassRegistry &);
+void initializeCSKYDAGToDAGISelPass(PassRegistry &);
} // namespace llvm
using namespace llvm;
#define DEBUG_TYPE "csky-isel"
+#define PASS_NAME "CSKY DAG->DAG Pattern Instruction Selection"
namespace {
class CSKYDAGToDAGISel : public SelectionDAGISel {
explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {}
- StringRef getPassName() const override {
- return "CSKY DAG->DAG Pattern Instruction Selection";
- }
-
bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through.
Subtarget = &MF.getSubtarget<CSKYSubtarget>();
char CSKYDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(CSKYDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
void CSKYDAGToDAGISel::Select(SDNode *N) {
// If we have a custom node, we have already selected
if (N->isMachineOpcode()) {
PassRegistry *Registry = PassRegistry::getPassRegistry();
initializeCSKYConstantIslandsPass(*Registry);
+ initializeCSKYDAGToDAGISelPass(*Registry);
}
static std::string computeDataLayout(const Triple &TT) {
namespace llvm {
class HexagonTargetMachine;
class ImmutablePass;
+ class PassRegistry;
/// Creates a Hexagon-specific Target Transformation Info pass.
ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM);
+
+ void initializeHexagonDAGToDAGISelPass(PassRegistry &);
} // end namespace llvm;
#endif
using namespace llvm;
#define DEBUG_TYPE "hexagon-isel"
+#define PASS_NAME "Hexagon DAG->DAG Pattern Instruction Selection"
static
cl::opt<bool>
char HexagonDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(HexagonDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
public:
static char ID;
+ HexagonDAGToDAGISel() = delete;
+
explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr),
inline bool SelectAnyImm2(SDValue &N, SDValue &R);
inline bool SelectAnyImm3(SDValue &N, SDValue &R);
- StringRef getPassName() const override {
- return "Hexagon DAG->DAG Pattern Instruction Selection";
- }
-
// Generate a machine instruction node corresponding to the circ/brev
// load intrinsic.
MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
void initializeHexagonPacketizerPass(PassRegistry&);
void initializeHexagonRDFOptPass(PassRegistry&);
void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
+ void initializeHexagonVExtractPass(PassRegistry &);
void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
- void initializeHexagonVExtractPass(PassRegistry&);
Pass *createHexagonLoopIdiomPass();
Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
initializeHexagonVectorCombineLegacyPass(PR);
initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
initializeHexagonVExtractPass(PR);
+ initializeHexagonDAGToDAGISelPass(PR);
}
HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
namespace llvm {
class FunctionPass;
class LanaiTargetMachine;
+class PassRegistry;
// createLanaiISelDag - This pass converts a legalized DAG into a
// Lanai-specific DAG, ready for instruction scheduling.
// operations.
FunctionPass *createLanaiSetflagAluCombinerPass();
+void initializeLanaiDAGToDAGISelPass(PassRegistry &);
+
} // namespace llvm
#endif // LLVM_LIB_TARGET_LANAI_LANAI_H
using namespace llvm;
#define DEBUG_TYPE "lanai-isel"
+#define PASS_NAME "Lanai DAG->DAG Pattern Instruction Selection"
//===----------------------------------------------------------------------===//
// Instruction Selector Implementation
public:
static char ID;
+ LanaiDAGToDAGISel() = delete;
+
explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine)
: SelectionDAGISel(ID, TargetMachine) {}
return SelectionDAGISel::runOnMachineFunction(MF);
}
- // Pass Name
- StringRef getPassName() const override {
- return "Lanai DAG->DAG Pattern Instruction Selection";
- }
-
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
std::vector<SDValue> &OutOps) override;
char LanaiDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(LanaiDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
// Helper functions for ComplexPattern used on LanaiInstrInfo
// Used on Lanai Load/Store instructions.
bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) {
// Register the target.
RegisterTargetMachine<LanaiTargetMachine> registered_target(
getTheLanaiTarget());
+ PassRegistry &PR = *PassRegistry::getPassRegistry();
+ initializeLanaiDAGToDAGISelPass(PR);
}
static std::string computeDataLayout() {
#include "llvm/Target/TargetMachine.h"
namespace llvm {
-class LoongArchTargetMachine;
class AsmPrinter;
class FunctionPass;
+class LoongArchTargetMachine;
class MCInst;
class MCOperand;
class MachineInstr;
MCOperand &MCOp,
const AsmPrinter &AP);
-FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM);
FunctionPass *createLoongArchExpandAtomicPseudoPass();
-void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &);
-
+FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM);
FunctionPass *createLoongArchPreRAExpandPseudoPass();
+void initializeLoongArchDAGToDAGISelPass(PassRegistry &);
+void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &);
void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &);
} // end namespace llvm
using namespace llvm;
#define DEBUG_TYPE "loongarch-isel"
+#define PASS_NAME "LoongArch DAG->DAG Pattern Instruction Selection"
char LoongArchDAGToDAGISel::ID;
+INITIALIZE_PASS(LoongArchDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
void LoongArchDAGToDAGISel::Select(SDNode *Node) {
// If we have a custom node, we have already selected.
if (Node->isMachineOpcode()) {
public:
static char ID;
+ LoongArchDAGToDAGISel() = delete;
+
explicit LoongArchDAGToDAGISel(LoongArchTargetMachine &TM)
: SelectionDAGISel(ID, TM) {}
- StringRef getPassName() const override {
- return "LoongArch DAG->DAG Pattern Instruction Selection";
- }
-
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<LoongArchSubtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
RegisterTargetMachine<LoongArchTargetMachine> Y(getTheLoongArch64Target());
auto *PR = PassRegistry::getPassRegistry();
initializeLoongArchPreRAExpandPseudoPass(*PR);
+ initializeLoongArchDAGToDAGISelPass(*PR);
}
static std::string computeDataLayout(const Triple &TT) {
class M68kRegisterBankInfo;
class M68kSubtarget;
class M68kTargetMachine;
+class PassRegistry;
/// This pass converts a legalized DAG into a M68k-specific DAG, ready for
/// instruction scheduling.
createM68kInstructionSelector(const M68kTargetMachine &, const M68kSubtarget &,
const M68kRegisterBankInfo &);
+void initializeM68kDAGToDAGISelPass(PassRegistry &);
+
} // namespace llvm
#endif // LLVM_LIB_TARGET_M68K_M68K_H
using namespace llvm;
#define DEBUG_TYPE "m68k-isel"
+#define PASS_NAME "M68k DAG->DAG Pattern Instruction Selection"
namespace {
public:
static char ID;
+ M68kDAGToDAGISel() = delete;
+
explicit M68kDAGToDAGISel(M68kTargetMachine &TM)
: SelectionDAGISel(ID, TM), Subtarget(nullptr) {}
- StringRef getPassName() const override {
- return "M68k DAG->DAG Pattern Instruction Selection";
- }
-
bool runOnMachineFunction(MachineFunction &MF) override;
bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
};
char M68kDAGToDAGISel::ID;
+
+INITIALIZE_PASS(M68kDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
} // namespace
bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
RegisterTargetMachine<M68kTargetMachine> X(getTheM68kTarget());
auto *PR = PassRegistry::getPassRegistry();
initializeGlobalISel(*PR);
+ initializeM68kDAGToDAGISelPass(*PR);
}
namespace {
}
namespace llvm {
- class MSP430TargetMachine;
- class FunctionPass;
+class FunctionPass;
+class MSP430TargetMachine;
+class PassRegistry;
- FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM,
+ CodeGenOpt::Level OptLevel);
- FunctionPass *createMSP430BranchSelectionPass();
+FunctionPass *createMSP430BranchSelectionPass();
-} // end namespace llvm;
+void initializeMSP430DAGToDAGISelPass(PassRegistry &);
+
+} // namespace llvm
#endif
using namespace llvm;
#define DEBUG_TYPE "msp430-isel"
+#define PASS_NAME "MSP430 DAG->DAG Pattern Instruction Selection"
namespace {
struct MSP430ISelAddressMode {
public:
static char ID;
+ MSP430DAGToDAGISel() = delete;
+
MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {}
private:
- StringRef getPassName() const override {
- return "MSP430 DAG->DAG Pattern Instruction Selection";
- }
-
bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
char MSP430DAGToDAGISel::ID;
+INITIALIZE_PASS(MSP430DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
/// createMSP430ISelDag - This pass converts a legalized DAG into a
/// MSP430-specific DAG, ready for instruction scheduling.
///
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Target() {
// Register the target.
RegisterTargetMachine<MSP430TargetMachine> X(getTheMSP430Target());
+ PassRegistry &PR = *PassRegistry::getPassRegistry();
+ initializeMSP430DAGToDAGISelPass(PR);
}
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
#include "llvm/Target/TargetMachine.h"
namespace llvm {
- class MipsTargetMachine;
- class ModulePass;
- class FunctionPass;
- class MipsRegisterBankInfo;
- class MipsSubtarget;
- class MipsTargetMachine;
- class InstructionSelector;
- class PassRegistry;
-
- ModulePass *createMipsOs16Pass();
- ModulePass *createMips16HardFloatPass();
-
- FunctionPass *createMipsModuleISelDagPass();
- FunctionPass *createMipsOptimizePICCallPass();
- FunctionPass *createMipsDelaySlotFillerPass();
- FunctionPass *createMipsBranchExpansion();
- FunctionPass *createMipsConstantIslandPass();
- FunctionPass *createMicroMipsSizeReducePass();
- FunctionPass *createMipsExpandPseudoPass();
- FunctionPass *createMipsPreLegalizeCombiner();
- FunctionPass *createMipsPostLegalizeCombiner(bool IsOptNone);
- FunctionPass *createMipsMulMulBugPass();
-
- InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &,
- MipsSubtarget &,
- MipsRegisterBankInfo &);
-
- void initializeMipsDelaySlotFillerPass(PassRegistry &);
- void initializeMipsBranchExpansionPass(PassRegistry &);
- void initializeMicroMipsSizeReducePass(PassRegistry &);
- void initializeMipsPreLegalizerCombinerPass(PassRegistry&);
- void initializeMipsPostLegalizerCombinerPass(PassRegistry &);
- void initializeMipsMulMulBugFixPass(PassRegistry&);
-} // end namespace llvm;
+class FunctionPass;
+class InstructionSelector;
+class MipsRegisterBankInfo;
+class MipsSubtarget;
+class MipsTargetMachine;
+class MipsTargetMachine;
+class ModulePass;
+class PassRegistry;
+
+ModulePass *createMipsOs16Pass();
+ModulePass *createMips16HardFloatPass();
+
+FunctionPass *createMipsModuleISelDagPass();
+FunctionPass *createMipsOptimizePICCallPass();
+FunctionPass *createMipsDelaySlotFillerPass();
+FunctionPass *createMipsBranchExpansion();
+FunctionPass *createMipsConstantIslandPass();
+FunctionPass *createMicroMipsSizeReducePass();
+FunctionPass *createMipsExpandPseudoPass();
+FunctionPass *createMipsPreLegalizeCombiner();
+FunctionPass *createMipsPostLegalizeCombiner(bool IsOptNone);
+FunctionPass *createMipsMulMulBugPass();
+
+InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &,
+ MipsSubtarget &,
+ MipsRegisterBankInfo &);
+
+void initializeMicroMipsSizeReducePass(PassRegistry &);
+void initializeMipsBranchExpansionPass(PassRegistry &);
+void initializeMipsDAGToDAGISelPass(PassRegistry &);
+void initializeMipsDelaySlotFillerPass(PassRegistry &);
+void initializeMipsMulMulBugFixPass(PassRegistry &);
+void initializeMipsPostLegalizerCombinerPass(PassRegistry &);
+void initializeMipsPreLegalizerCombinerPass(PassRegistry &);
+} // namespace llvm
#endif
using namespace llvm;
#define DEBUG_TYPE "mips-isel"
+#define PASS_NAME "MIPS DAG->DAG Pattern Instruction Selection"
//===----------------------------------------------------------------------===//
// Instruction Selector Implementation
}
char MipsDAGToDAGISel::ID = 0;
+
+INITIALIZE_PASS(MipsDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
public:
static char ID;
+ MipsDAGToDAGISel() = delete;
+
explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
: SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {}
- // Pass Name
- StringRef getPassName() const override {
- return "MIPS DAG->DAG Pattern Instruction Selection";
- }
-
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override;
initializeMipsPreLegalizerCombinerPass(*PR);
initializeMipsPostLegalizerCombinerPass(*PR);
initializeMipsMulMulBugFixPass(*PR);
+ initializeMipsDAGToDAGISelPass(*PR);
}
static std::string computeDataLayout(const Triple &TT, StringRef CPU,
#include "llvm/Support/CodeGen.h"
namespace llvm {
-class NVPTXTargetMachine;
class FunctionPass;
class MachineFunctionPass;
+class NVPTXTargetMachine;
+class PassRegistry;
namespace NVPTXCC {
enum CondCodes {
};
}
}
-} // end namespace llvm;
+void initializeNVPTXDAGToDAGISelPass(PassRegistry &);
+} // namespace llvm
// Defines symbolic names for NVPTX registers. This defines a mapping from
// register name to register number.
using namespace llvm;
#define DEBUG_TYPE "nvptx-isel"
+#define PASS_NAME "NVPTX DAG->DAG Pattern Instruction Selection"
/// createNVPTXISelDag - This pass converts a legalized DAG into a
/// NVPTX-specific DAG, ready for instruction scheduling.
char NVPTXDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(NVPTXDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, tm, OptLevel), TM(tm) {
public:
static char ID;
+ NVPTXDAGToDAGISel() = delete;
+
explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
CodeGenOpt::Level OptLevel);
- // Pass Name
- StringRef getPassName() const override {
- return "NVPTX DAG->DAG Pattern Instruction Selection";
- }
bool runOnMachineFunction(MachineFunction &MF) override;
const NVPTXSubtarget *Subtarget = nullptr;
namespace llvm {
-void initializeNVVMIntrRangePass(PassRegistry&);
-void initializeNVVMReflectPass(PassRegistry&);
void initializeGenericToNVVMPass(PassRegistry&);
void initializeNVPTXAllocaHoistingPass(PassRegistry &);
-void initializeNVPTXAtomicLowerPass(PassRegistry &);
void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
+void initializeNVPTXAtomicLowerPass(PassRegistry &);
void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
-void initializeNVPTXLowerArgsPass(PassRegistry &);
void initializeNVPTXLowerAllocaPass(PassRegistry &);
+void initializeNVPTXLowerArgsPass(PassRegistry &);
void initializeNVPTXProxyRegErasurePass(PassRegistry &);
+void initializeNVVMIntrRangePass(PassRegistry &);
+void initializeNVVMReflectPass(PassRegistry &);
} // end namespace llvm
initializeNVPTXLowerAllocaPass(PR);
initializeNVPTXLowerAggrCopiesPass(PR);
initializeNVPTXProxyRegErasurePass(PR);
+ initializeNVPTXDAGToDAGISelPass(PR);
}
static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) {
void initializePPCMIPeepholePass(PassRegistry&);
void initializePPCExpandAtomicPseudoPass(PassRegistry &);
void initializePPCCTRLoopsPass(PassRegistry &);
+ void initializePPCDAGToDAGISelPass(PassRegistry &);
extern char &PPCVSXFMAMutateID;
using namespace llvm;
#define DEBUG_TYPE "ppc-codegen"
+#define PASS_NAME "PowerPC DAG->DAG Pattern Instruction Selection"
STATISTIC(NumSextSetcc,
"Number of (sext(setcc)) nodes expanded into GPR sequence.");
public:
static char ID;
+ PPCDAGToDAGISel() = delete;
+
explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, tm, OptLevel), TM(tm) {}
return true;
}
- StringRef getPassName() const override {
- return "PowerPC DAG->DAG Pattern Instruction Selection";
- }
-
// Include the pieces autogenerated from the target description.
#include "PPCGenDAGISel.inc"
char PPCDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(PPCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
/// getGlobalBaseReg - Output the instructions required to put the
/// base address to use for accessing globals into a register.
///
initializePPCExpandAtomicPseudoPass(PR);
initializeGlobalISel(PR);
initializePPCCTRLoopsPass(PR);
+ initializePPCDAGToDAGISelPass(PR);
}
static bool isLittleEndianTriple(const Triple &T) {
#include "llvm/Target/TargetMachine.h"
namespace llvm {
-class RISCVRegisterBankInfo;
-class RISCVSubtarget;
-class RISCVTargetMachine;
class AsmPrinter;
class FunctionPass;
class InstructionSelector;
class MachineInstr;
class MachineOperand;
class PassRegistry;
+class RISCVRegisterBankInfo;
+class RISCVSubtarget;
+class RISCVTargetMachine;
FunctionPass *createRISCVCodeGenPreparePass();
void initializeRISCVCodeGenPreparePass(PassRegistry &);
InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
RISCVSubtarget &,
RISCVRegisterBankInfo &);
-}
+void initializeRISCVDAGToDAGISelPass(PassRegistry &);
+} // namespace llvm
#endif
using namespace llvm;
#define DEBUG_TYPE "riscv-isel"
+#define PASS_NAME "RISCV DAG->DAG Pattern Instruction Selection"
namespace llvm::RISCV {
#define GET_RISCVVSSEGTable_IMPL
}
char RISCVDAGToDAGISel::ID = 0;
+
+INITIALIZE_PASS(RISCVDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
public:
static char ID;
+ RISCVDAGToDAGISel() = delete;
+
explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, TargetMachine, OptLevel) {}
- StringRef getPassName() const override {
- return "RISCV DAG->DAG Pattern Instruction Selection";
- }
-
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<RISCVSubtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
initializeRISCVPreRAExpandPseudoPass(*PR);
initializeRISCVExpandPseudoPass(*PR);
initializeRISCVInsertVSETVLIPass(*PR);
+ initializeRISCVDAGToDAGISelPass(*PR);
}
static StringRef computeDataLayout(const Triple &TT) {
#include "llvm/Target/TargetMachine.h"
namespace llvm {
- class FunctionPass;
- class SparcTargetMachine;
- class AsmPrinter;
- class MCInst;
- class MachineInstr;
+class AsmPrinter;
+class FunctionPass;
+class MCInst;
+class MachineInstr;
+class PassRegistry;
+class SparcTargetMachine;
- FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
- FunctionPass *createSparcDelaySlotFillerPass();
+FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
+FunctionPass *createSparcDelaySlotFillerPass();
- void LowerSparcMachineInstrToMCInst(const MachineInstr *MI,
- MCInst &OutMI,
- AsmPrinter &AP);
-} // end namespace llvm;
+void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
+ AsmPrinter &AP);
+void initializeSparcDAGToDAGISelPass(PassRegistry &);
+} // namespace llvm
namespace llvm {
// Enums corresponding to Sparc condition codes, both icc's and fcc's. These
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+#define DEBUG_TYPE "sparc-isel"
+#define PASS_NAME "SPARC DAG->DAG Pattern Instruction Selection"
+
//===----------------------------------------------------------------------===//
// Instruction Selector Implementation
//===----------------------------------------------------------------------===//
public:
static char ID;
+ SparcDAGToDAGISel() = delete;
+
explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(ID, tm) {}
bool runOnMachineFunction(MachineFunction &MF) override {
unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
- StringRef getPassName() const override {
- return "SPARC DAG->DAG Pattern Instruction Selection";
- }
-
// Include the pieces autogenerated from the target description.
#include "SparcGenDAGISel.inc"
char SparcDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(SparcDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
return CurDAG->getRegister(GlobalBaseReg,
RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
+
+ PassRegistry &PR = *PassRegistry::getPassRegistry();
+ initializeSparcDAGToDAGISelPass(PR);
}
static std::string computeDataLayout(const Triple &T, bool is64Bit) {
#include "llvm/Support/CodeGen.h"
namespace llvm {
-class SystemZTargetMachine;
class FunctionPass;
class PassRegistry;
+class SystemZTargetMachine;
namespace SystemZ {
// Condition-code mask values.
FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM);
FunctionPass *createSystemZTDCPass();
+void initializeSystemZCopyPhysRegsPass(PassRegistry &);
+void initializeSystemZDAGToDAGISelPass(PassRegistry &);
void initializeSystemZElimComparePass(PassRegistry &);
-void initializeSystemZShortenInstPass(PassRegistry &);
-void initializeSystemZLongBranchPass(PassRegistry &);
void initializeSystemZLDCleanupPass(PassRegistry &);
-void initializeSystemZCopyPhysRegsPass(PassRegistry &);
+void initializeSystemZLongBranchPass(PassRegistry &);
void initializeSystemZPostRewritePass(PassRegistry &);
+void initializeSystemZShortenInstPass(PassRegistry &);
void initializeSystemZTDCPassPass(PassRegistry &);
} // end namespace llvm
using namespace llvm;
#define DEBUG_TYPE "systemz-isel"
+#define PASS_NAME "SystemZ DAG->DAG Pattern Instruction Selection"
namespace {
// Used to build addressing modes.
public:
static char ID;
+ SystemZDAGToDAGISel() = delete;
+
SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {}
return SelectionDAGISel::runOnMachineFunction(MF);
}
- // Override MachineFunctionPass.
- StringRef getPassName() const override {
- return "SystemZ DAG->DAG Pattern Instruction Selection";
- }
-
// Override SelectionDAGISel.
void Select(SDNode *Node) override;
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
char SystemZDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(SystemZDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new SystemZDAGToDAGISel(TM, OptLevel);
initializeSystemZShortenInstPass(PR);
initializeSystemZPostRewritePass(PR);
initializeSystemZTDCPassPass(PR);
+ initializeSystemZDAGToDAGISelPass(PR);
}
static std::string computeDataLayout(const Triple &TT) {
#include "llvm/Target/TargetMachine.h"
namespace llvm {
-class FunctionPass;
-class VETargetMachine;
class AsmPrinter;
+class FunctionPass;
class MCInst;
class MachineInstr;
+class PassRegistry;
+class VETargetMachine;
FunctionPass *createVEISelDag(VETargetMachine &TM);
FunctionPass *createLVLGenPass();
+void initializeVEDAGToDAGISelPass(PassRegistry &);
void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP);
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+#define DEBUG_TYPE "ve-isel"
+#define PASS_NAME "VE DAG->DAG Pattern Instruction Selection"
+
//===--------------------------------------------------------------------===//
/// VEDAGToDAGISel - VE specific code to select VE machine
/// instructions for SelectionDAG operations.
public:
static char ID;
+ VEDAGToDAGISel() = delete;
+
explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {}
bool runOnMachineFunction(MachineFunction &MF) override {
unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
- StringRef getPassName() const override {
- return "VE DAG->DAG Pattern Instruction Selection";
- }
-
// Include the pieces autogenerated from the target description.
#include "VEGenDAGISel.inc"
char VEDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(VEDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::FrameIndex)
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETarget() {
// Register the target.
RegisterTargetMachine<VETargetMachine> X(getTheVETarget());
+
+ PassRegistry &PR = *PassRegistry::getPassRegistry();
+ initializeVEDAGToDAGISelPass(PR);
}
static std::string computeDataLayout(const Triple &T) {
ModulePass *createWebAssemblyMCLowerPrePass();
// PassRegistry initialization declarations.
-void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &);
-void initializeWebAssemblyLowerEmscriptenEHSjLjPass(PassRegistry &);
void initializeFixFunctionBitcastsPass(PassRegistry &);
void initializeOptimizeReturnedPass(PassRegistry &);
+void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &);
void initializeWebAssemblyArgumentMovePass(PassRegistry &);
-void initializeWebAssemblySetP2AlignOperandsPass(PassRegistry &);
-void initializeWebAssemblyReplacePhysRegsPass(PassRegistry &);
-void initializeWebAssemblyNullifyDebugValueListsPass(PassRegistry &);
-void initializeWebAssemblyOptimizeLiveIntervalsPass(PassRegistry &);
-void initializeWebAssemblyMemIntrinsicResultsPass(PassRegistry &);
-void initializeWebAssemblyRegStackifyPass(PassRegistry &);
-void initializeWebAssemblyRegColoringPass(PassRegistry &);
-void initializeWebAssemblyFixBrTableDefaultsPass(PassRegistry &);
-void initializeWebAssemblyFixIrreducibleControlFlowPass(PassRegistry &);
-void initializeWebAssemblyLateEHPreparePass(PassRegistry &);
-void initializeWebAssemblyExceptionInfoPass(PassRegistry &);
void initializeWebAssemblyCFGSortPass(PassRegistry &);
void initializeWebAssemblyCFGStackifyPass(PassRegistry &);
+void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &);
+void initializeWebAssemblyDebugFixupPass(PassRegistry &);
+void initializeWebAssemblyExceptionInfoPass(PassRegistry &);
void initializeWebAssemblyExplicitLocalsPass(PassRegistry &);
+void initializeWebAssemblyFixBrTableDefaultsPass(PassRegistry &);
+void initializeWebAssemblyFixIrreducibleControlFlowPass(PassRegistry &);
+void initializeWebAssemblyLateEHPreparePass(PassRegistry &);
void initializeWebAssemblyLowerBrUnlessPass(PassRegistry &);
-void initializeWebAssemblyRegNumberingPass(PassRegistry &);
-void initializeWebAssemblyDebugFixupPass(PassRegistry &);
-void initializeWebAssemblyPeepholePass(PassRegistry &);
-void initializeWebAssemblyMCLowerPrePassPass(PassRegistry &);
+void initializeWebAssemblyLowerEmscriptenEHSjLjPass(PassRegistry &);
void initializeWebAssemblyLowerRefTypesIntPtrConvPass(PassRegistry &);
+void initializeWebAssemblyMCLowerPrePassPass(PassRegistry &);
+void initializeWebAssemblyMemIntrinsicResultsPass(PassRegistry &);
+void initializeWebAssemblyNullifyDebugValueListsPass(PassRegistry &);
+void initializeWebAssemblyOptimizeLiveIntervalsPass(PassRegistry &);
+void initializeWebAssemblyPeepholePass(PassRegistry &);
+void initializeWebAssemblyRegColoringPass(PassRegistry &);
+void initializeWebAssemblyRegNumberingPass(PassRegistry &);
+void initializeWebAssemblyRegStackifyPass(PassRegistry &);
+void initializeWebAssemblyReplacePhysRegsPass(PassRegistry &);
+void initializeWebAssemblySetP2AlignOperandsPass(PassRegistry &);
namespace WebAssembly {
enum TargetIndex {
using namespace llvm;
#define DEBUG_TYPE "wasm-isel"
+#define PASS_NAME "WebAssembly Instruction Selection"
//===--------------------------------------------------------------------===//
/// WebAssembly-specific code to select WebAssembly machine instructions for
public:
static char ID;
+ WebAssemblyDAGToDAGISel() = delete;
+
WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM,
CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
- StringRef getPassName() const override {
- return "WebAssembly Instruction Selection";
- }
-
bool runOnMachineFunction(MachineFunction &MF) override {
LLVM_DEBUG(dbgs() << "********** ISelDAGToDAG **********\n"
"********** Function: "
char WebAssemblyDAGToDAGISel::ID;
+INITIALIZE_PASS(WebAssemblyDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
void WebAssemblyDAGToDAGISel::PreprocessISelDAG() {
// Stack objects that should be allocated to locals are hoisted to WebAssembly
// locals when they are first used. However for those without uses, we hoist
initializeWebAssemblyMCLowerPrePassPass(PR);
initializeWebAssemblyLowerRefTypesIntPtrConvPass(PR);
initializeWebAssemblyFixBrTableDefaultsPass(PR);
+ initializeWebAssemblyDAGToDAGISelPass(PR);
}
//===----------------------------------------------------------------------===//
namespace llvm {
class FunctionPass;
class ModulePass;
+ class PassRegistry;
class TargetMachine;
class XCoreTargetMachine;
FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM,
CodeGenOpt::Level OptLevel);
ModulePass *createXCoreLowerThreadLocalPass();
+ void initializeXCoreDAGToDAGISelPass(PassRegistry &);
} // end namespace llvm;
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+#define DEBUG_TYPE "xcore-isel"
+#define PASS_NAME "XCore DAG->DAG Pattern Instruction Selection"
+
/// XCoreDAGToDAGISel - XCore specific code to select XCore machine
/// instructions for SelectionDAG operations.
///
public:
static char ID;
+ XCoreDAGToDAGISel() = delete;
+
XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {}
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
- StringRef getPassName() const override {
- return "XCore DAG->DAG Pattern Instruction Selection";
- }
-
// Include the pieces autogenerated from the target description.
#include "XCoreGenDAGISel.inc"
};
char XCoreDAGToDAGISel::ID = 0;
+INITIALIZE_PASS(XCoreDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
/// createXCoreISelDag - This pass converts a legalized DAG into a
/// XCore-specific DAG, ready for instruction scheduling.
///
// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() {
RegisterTargetMachine<XCoreTargetMachine> X(getTheXCoreTarget());
+ PassRegistry &PR = *PassRegistry::getPassRegistry();
+ initializeXCoreDAGToDAGISelPass(PR);
}
TargetTransformInfo