[arm] Add new isa quirk bit for Cortex-M3 ldrd issue.

With the new data structures it is trivial to add a new field and we
aren't (too) limited as to the number we have.  This patch adds a new
bit to describe the need for a particular compiler behaviour
modification: in this case a quirk in the cortex-m3.

	* arm-isa.h (enum isa_feature): Add isa_quirk_cm3_ldrd.
	(ISA_ALL_QUIRKS): New macro.
	* arm-cores.def (cortex-m3): Add isa_quirk_cm3_ldrd to isa feature list.
	* arm.c (isa_quirkbits): New feature-list bitmap.
	(arm_configure_build_target): Ignore quirk bits when comparing an
	architecture feature list with a CPU feature list.
	(arm_option_override): Initialize_isa_quirkbits.  If the user has
	not specified -m[no-]fix-cortex-m3-ldrd, automatically enable the
	feature if isa_quirk_cm3_ldrd appears in the isa feature list.

From-SVN: r243701

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4202c77..659439c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,17 @@
 2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
 
+       * arm-isa.h (enum isa_feature): Add isa_quirk_cm3_ldrd.
+       (ISA_ALL_QUIRKS): New macro.
+       * arm-cores.def (cortex-m3): Add isa_quirk_cm3_ldrd to isa feature list.
+       * arm.c (isa_quirkbits): New feature-list bitmap.
+       (arm_configure_build_target): Ignore quirk bits when comparing an
+       architecture feature list with a CPU feature list.
+       (arm_option_override): Initialize_isa_quirkbits.  If the user has
+       not specified -m[no-]fix-cortex-m3-ldrd, automatically enable the
+       feature if isa_quirk_cm3_ldrd appears in the isa feature list.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
        * arm.c (arm_option_override): Use arm_active_target as source of
        information for arm_base_arch and arm_arch_name.
        * (arm_file_start): Use arm_active_target for core name.

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 7c951f3..7f64a1f 100644 (file)
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -160,7 +160,7 @@ ARM_CORE("cortex-r7",               cortexr7, cortexr7,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv
 ARM_CORE("cortex-r8",          cortexr8, cortexr7,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
 ARM_CORE("cortex-m7",          cortexm7, cortexm7,             TF_LDSCHED,       7EM,  ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
 ARM_CORE("cortex-m4",          cortexm4, cortexm4,             TF_LDSCHED,       7EM,  ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
-ARM_CORE("cortex-m3",          cortexm3, cortexm3,             TF_LDSCHED,       7M,   ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
+ARM_CORE("cortex-m3",          cortexm3, cortexm3,             TF_LDSCHED,       7M,   ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
 ARM_CORE("marvell-pj4",                marvell_pj4, marvell_pj4,       TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
 
 /* V7 big.LITTLE implementations */

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3806226..c6be4d8 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3056,6 +3056,7 @@ arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
 }
 
 static sbitmap isa_fpubits;
+static sbitmap isa_quirkbits;
 
 /* Configure a build target TARGET from the user-specified options OPTS and
    OPTS_SET.  If WARN_COMPATIBLE, emit a diagnostic if both the CPU and
@@ -3097,6 +3098,8 @@ arm_configure_build_target (struct arm_build_target *target,
 
          arm_initialize_isa (cpu_isa, arm_selected_cpu->isa_bits);
          bitmap_xor (cpu_isa, cpu_isa, target->isa);
+         /* Ignore any bits that are quirk bits.  */
+         bitmap_and_compl (cpu_isa, cpu_isa, isa_quirkbits);
          /* Ignore (for now) any bits that might be set by -mfpu.  */
          bitmap_and_compl (cpu_isa, cpu_isa, isa_fpubits);
 
@@ -3263,6 +3266,10 @@ static void
 arm_option_override (void)
 {
   static const enum isa_feature fpu_bitlist[] = { ISA_ALL_FPU, isa_nobit };
+  static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit};
+
+  isa_quirkbits = sbitmap_alloc (isa_num_bits);
+  arm_initialize_isa (isa_quirkbits, quirk_bitlist);
 
   isa_fpubits = sbitmap_alloc (isa_num_bits);
   arm_initialize_isa (isa_fpubits, fpu_bitlist);
@@ -3510,7 +3517,7 @@ arm_option_override (void)
   /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores.  */
   if (fix_cm3_ldrd == 2)
     {
-      if (arm_selected_cpu->core == TARGET_CPU_cortexm3)
+      if (bitmap_bit_p (arm_active_target.isa, isa_quirk_cm3_ldrd))
        fix_cm3_ldrd = 1;
       else
        fix_cm3_ldrd = 0;